2017 Panhellenic Conference on Electronics and Telecommunications (PACET)最新文献_第4页

Investigation of the operational behavior of a DC/DC high step up R2P2 converter DC/DC高升压R2P2变换器工作特性的研究

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259957

Marianthi N. Pefkianaki, C. Zogogianni, E. Tatakis

引用次数: 2

Less is more: Increasing the scope of hardware debugging with compression 少即是多:通过压缩增加硬件调试的范围

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259958

Fotis Kostarelos, George Charitopoulos, D. Pnevmatikatos

{"title":"Less is more: Increasing the scope of hardware debugging with compression","authors":"Fotis Kostarelos, George Charitopoulos, D. Pnevmatikatos","doi":"10.1109/PACET.2017.8259958","DOIUrl":"https://doi.org/10.1109/PACET.2017.8259958","url":null,"abstract":"In this work we consider the slow and tedious phase of hardware debugging in FPGAs. The process of hardware debugging is normally done via Internal Logic Analyzer (ILA) circuits, which add user observability in internal FPGA signals. The user first defines the target for debugging signal and a triggering condition. Then the ILA stores traces of it in trace buffers, these traces are finally transferred to a host PC for the user to observe. The user also has to consider the limited FPGA memory resources, which result in small-sized trace buffers, an important restriction of hardware debugging. In this paper, we attempt to increase the scope of hardware tracing, i.e. the number of samples written on the trace buffers, with the use of compression. We use the LZW algorithm and find that we can increase the debugging signals number of recorded samples by 90%, i.e. have double the amount of useful data with the same memory usage. On the memory plane we conclude that, for the same number of recorded samples, our architecture uses less than half the resources compared to the standard Xilinx ILA block for signal tracing.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127533101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A VHDL implementation of the Hummingbird cryptographic algorithm 一个VHDL实现的蜂鸟密码算法

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259979

Stavroula Mammou, D. Balobas, Nikos Konofaos

引用次数: 1

Implementation of an all-optical buffer & TimeSlot-interchanger based on integrated SOI delay lines 基于集成SOI延迟线的全光缓冲器和时隙交换器的实现

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259961

G. Mourgias-Alexandris, M. Moralis‐Pegios, N. Terzenidis, N. Pleros, K. Vyrsokinos

引用次数: 0

Towards an analytical description of a TaO memristor 对TaO忆阻器的分析描述

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259948

A. Ascoli, R. Tetzlaff, V. Ntinas, G. Sirakoulis

{"title":"Towards an analytical description of a TaO memristor","authors":"A. Ascoli, R. Tetzlaff, V. Ntinas, G. Sirakoulis","doi":"10.1109/PACET.2017.8259948","DOIUrl":"https://doi.org/10.1109/PACET.2017.8259948","url":null,"abstract":"Memristors promise to revolutionise the world of electronics in the years to come. Besides their most popular applications in the fields of non-volatile memory design and neuro-morphic system development, their ability to process signals and store data in the same physical location may allow the conception of novel mem-computing machines outperforming state-of-the-art hardware systems suffering from the Von Neumann bottleneck. The complexity of real-world memristor models, capturing the inherent nonlinearity of the switching kinetics of the nanodevices, is one of the obstacles towards an extensive exploration of the full potential of memristors in nanoelectronics. It is well-known, in fact, that serious convergence issues frequently arise in the numerical simulation of the differential algebraic equation sets modelling the dynamics of real-world memristors. In this work we propose a strategy to develop a general closed-form mathematical representation of a real-world voltage-controlled memristor manufactured by Hewlett Packard Enterprise. The study aims to derive an analytical formula for the memductance of the nano-device under a general voltage input, starting off from the DC case. This research should be of great benefit to circuit designers, which typically use analytical formulas for the first hands-on calculations in the search for circuit topologies satisfying a certain set of specifications.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126609387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient coupling between thin-film plasmonic and SiN photonic waveguide 薄膜等离子体与光子波导的高效耦合

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259959

E. Chatzianagnostou, G. Dabos, D. Ketzaki, D. Tsiokos, N. Pleros

{"title":"Efficient coupling between thin-film plasmonic and SiN photonic waveguide","authors":"E. Chatzianagnostou, G. Dabos, D. Ketzaki, D. Tsiokos, N. Pleros","doi":"10.1109/PACET.2017.8259959","DOIUrl":"https://doi.org/10.1109/PACET.2017.8259959","url":null,"abstract":"Bringing photonics and electronics into a common integration platform can unleash unprecedented performance capabilities in data communication and sensing applications. Plasmonics were proposed as the key technology that can merge ultra-fast photonics and low-dimension electronics due to their metallic nature and their unique ability to guide light at subwavelength scales. However, inherent high losses of plasmonics impede their practical deployment in PICs. To ameliorate this limitation, selective integration of individual nano-plasmonic devices on low-loss photonic platforms is considered, allowing for enhanced chip-scale functionalities with realistic power budgets. Likewise, highly-efficient and fabrication-tolerant optical interfaces for co-planar plasmonic and photonic waveguides become essential, bridging these two “worlds” and ease combined high-volume manufacturing. In this work, a TM-mode butt-coupled interface for stoichiometric Si3N4 and gold-based thin-film plasmonic waveguides is proposed aiming to be utilized for bio-sensing applications. Following a systematic design process, this new configuration has been analyzed through 3D FDTD numerical simulations demonstrating interface insertion losses of 2dB at the wavelength of 1550 nm, with increased fabrication tolerance compared to silicon based waveguide alternatives.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130086401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A wireless three dimensional printer for printed circuit board applications 用于印刷电路板应用的无线三维打印机

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259976

George Isaakidis, Antonis Spiropoulos, M. Drakaki

引用次数: 0

Multilevel inverters for motor drives and wireless power transfer applications 用于电机驱动和无线电力传输应用的多电平逆变器

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259952

Dimitris Baros, Konstantinos Bampouras, Parthena Apostolidou, Evangelos Ioannou, N. Papanikolaou

引用次数: 7

Experimental survey on active thermoelectric cooling driven by PWM techniques PWM技术驱动的热电主动冷却实验研究

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259954

A. Boubaris, E. Karampasis, D. Voglitsis, N. Papanikolaou

引用次数: 3

An extended study of extreme multistability in a memristive circuit 忆阻电路中极端多稳定性的扩展研究

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259992

D. Prousalis, C. Volos, I. Stouboulos, I. Kyprianidis, D. Frantzeskakis

引用次数: 1