Towards an analytical description of a TaO memristor

Abstract

Memristors promise to revolutionise the world of electronics in the years to come. Besides their most popular applications in the fields of non-volatile memory design and neuro-morphic system development, their ability to process signals and store data in the same physical location may allow the conception of novel mem-computing machines outperforming state-of-the-art hardware systems suffering from the Von Neumann bottleneck. The complexity of real-world memristor models, capturing the inherent nonlinearity of the switching kinetics of the nanodevices, is one of the obstacles towards an extensive exploration of the full potential of memristors in nanoelectronics. It is well-known, in fact, that serious convergence issues frequently arise in the numerical simulation of the differential algebraic equation sets modelling the dynamics of real-world memristors. In this work we propose a strategy to develop a general closed-form mathematical representation of a real-world voltage-controlled memristor manufactured by Hewlett Packard Enterprise. The study aims to derive an analytical formula for the memductance of the nano-device under a general voltage input, starting off from the DC case. This research should be of great benefit to circuit designers, which typically use analytical formulas for the first hands-on calculations in the search for circuit topologies satisfying a certain set of specifications.