Real number modeling of a flash ADC using SystemVerilog

Abstract

Real Number Modeling (RNM) is the process of modeling an analog circuit's behavior as signal flow model. This means that every output of an analog component is sampled, in a discrete manner, from the inputs and the internal state. The model detects an event and decides the time to carry out a computation. A SystemVerilog behavioral real number model for a 3-bit flash analog-to-digital converter (ADC) is presented, in order to improve simulation efficiency. The ADC model simulation time completes in only 1.23s, which can be utilized effectively in high-frequency applications. The proposed model is compared to three different models: a transistor-level flash ADC, a Verilog-A ADC model and a Verilog-AMS with wreal ADC model. 65nm CMOS technology library was used for the flash ADC designs in Cadence Virtuoso. The simulation runs took place in Spectre (for transistor-level SPICE model) and AMS Simulator (for SystemVerilog, Verilog-A and Verilog-AMS with wreal). In all cases, the presented SystemVerilog model displays reduced simulation run time, in comparison with the other models, along with satisfying accuracy.