Lazaros Spyridopoulos, Nikos Konofaos, Theodoras Simopoulos, G. Alexiou
{"title":"ram上的横杆扇区寻址方案","authors":"Lazaros Spyridopoulos, Nikos Konofaos, Theodoras Simopoulos, G. Alexiou","doi":"10.1109/PACET.2017.8259951","DOIUrl":null,"url":null,"abstract":"Typical memory addressing, where a row of cells that forms the memory word, is addressed every time the memory is accessed, has the disadvantage of decreased addressing flexibility, originating from the strict addressing method and leading to addressing limitations. In this work we present and implement the crossbar addressing scheme, where the memory is addressed in a two dimensional way, using two decoders on each direction. Although crossbar addressing is mentioned on references there is no known implementation on SRAM memories. We extend this scheme proposing the new Sector addressing scheme, based on crossbar addressing.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Crossbar sector addressing scheme on SRAMs\",\"authors\":\"Lazaros Spyridopoulos, Nikos Konofaos, Theodoras Simopoulos, G. Alexiou\",\"doi\":\"10.1109/PACET.2017.8259951\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Typical memory addressing, where a row of cells that forms the memory word, is addressed every time the memory is accessed, has the disadvantage of decreased addressing flexibility, originating from the strict addressing method and leading to addressing limitations. In this work we present and implement the crossbar addressing scheme, where the memory is addressed in a two dimensional way, using two decoders on each direction. Although crossbar addressing is mentioned on references there is no known implementation on SRAM memories. We extend this scheme proposing the new Sector addressing scheme, based on crossbar addressing.\",\"PeriodicalId\":171095,\"journal\":{\"name\":\"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACET.2017.8259951\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACET.2017.8259951","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Typical memory addressing, where a row of cells that forms the memory word, is addressed every time the memory is accessed, has the disadvantage of decreased addressing flexibility, originating from the strict addressing method and leading to addressing limitations. In this work we present and implement the crossbar addressing scheme, where the memory is addressed in a two dimensional way, using two decoders on each direction. Although crossbar addressing is mentioned on references there is no known implementation on SRAM memories. We extend this scheme proposing the new Sector addressing scheme, based on crossbar addressing.