2018 IEEE International Conference on Rebooting Computing (ICRC)最新文献_第2页

Thermodynamic Intelligence, a Heretical Theory 热力学智能，一个异端理论

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/ICRC.2018.8638594

N. Ganesh

{"title":"Thermodynamic Intelligence, a Heretical Theory","authors":"N. Ganesh","doi":"10.1109/ICRC.2018.8638594","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638594","url":null,"abstract":"There is a significant amount of interest in the field of big data and machine learning right now. This has been driven by use of sophisticated learning algorithms along with large datasets and powerful computing hardware to achieve extraordinary success in narrow tasks. Such success has been classified as narrow artificial intelligence (AI), in order to distinguish it from general intelligence, which continues to be the holy grail of computing. If we are to progress from narrow to general AI, it is important to have a better understanding of what intelligence is and what it entails. As we seek to reboot computing across the stack, this is an important question to address, to help us identify the optimal devices, architectures and design techniques that will allow us to build the intelligent systems of the future. In this paper, I will review the fundamental ideas and assumptions that have allowed us to achieve computing in artificial systems over the years. Building off these ideas, I will discuss the important distinction between a good example of a system with general intelligence i.e. ourselves, and the intelligence achieved through our current computational approaches. Following this, I will use recent results to explore a new framework - a physically grounded theory of thermodynamic intelligence, and discuss the design paradigm that seeks to achieve such intelligence in systems.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115746451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Regular Expression Matching with Memristor TCAMs 忆阻器tcam的正则表达式匹配

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/ICRC.2018.8638603

Catherine E. Graves, W. Ma, X. Sheng, B. Buchanan, Le Zheng, Sity Lam, Xuema Li, S. R. Chalamalasetti, Lennie Kiyama, M. Foltin, Matthew P. Hardy, J. Strachan

{"title":"Regular Expression Matching with Memristor TCAMs","authors":"Catherine E. Graves, W. Ma, X. Sheng, B. Buchanan, Le Zheng, Sity Lam, Xuema Li, S. R. Chalamalasetti, Lennie Kiyama, M. Foltin, Matthew P. Hardy, J. Strachan","doi":"10.1109/ICRC.2018.8638603","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638603","url":null,"abstract":"Regular expression (RegEx)matching is a key function in network security, where matching of packet data against known malicious signatures filters and alerts against active network intrusions. RegExs are widely used in open source and commercial network security systems as they easily and concisely represent complex patterns like those malicious signatures. However, the latency and power required to perform RegEx matching is incredibly high and approaches to this problem struggle to achieve > 1 Gbps on real-world rulesets while internet wirespeeds continue to increase > 100 Gbps. We propose performing RegEx matching using memristor-based ternary content addressable memories (mTCAMs)with compressed finite automata (CFA)to meet this challenge. In this work, we show fabrication of mTCAM circuits with excellent device properties from 100nm to 20nm device sizes and validate mTCAM operation. SPICE simulations investigate mTCAM performance at scale and a mTCAM dynamic power model using 16nm mTCAM layout parameters demonstrates 0.173 fJ/bit/search energy for a $36times 250$ mTCAM array. Using a tiled architecture to implement a Snort ruleset, we estimate performance of our mTCAM approach to be 47.2 Gbps at 1.21W dynamic search power (39 Gbps/W), compared to a state-of-the-art FPGA approach which achieves 3.9 Gbps at 630mW (6.2 Gbps/W). Preliminary error analysis shows the mTCAM approach allows for arbitrarily low false positive/negative rates using minimal and standard state refresh techniques. Dynamic search power is also calculated prior to applying standard TCAM power-reduction techniques capable of lowering power by $simtimes 10$, further demonstrating the promise of mTCAM for wirespeed RegEx matching at low power.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"44 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Design of Superconducting Optoelectronic Networks for Neuromorphic Computing 用于神经形态计算的超导光电网络设计

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/ICRC.2018.8638595

S. Buckley, A. McCaughan, J. Chiles, R. Mirin, S. Nam, J. Shainline, Grant Bruer, J. Plank, Catherine D. Schuman

引用次数: 15

2018 IEEE International Conference on Rebooting Computing, ICRC 2018, McLean, VA, USA, November 7-9, 2018 2018 IEEE计算机重启国际会议，红十字国际委员会2018，美国弗吉尼亚州麦克莱恩，2018年11月7日至9日

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/icrc.2018.8638615

引用次数: 0

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics 基于集成纳米光子学的大扇入光逻辑电路多级优化

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/ICRC.2018.8638607

Takumi Egawa, T. Ishihara, H. Onodera, A. Shinya, S. Kita, K. Nozaki, K. Takata, M. Notomi

引用次数: 1

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks SNRA:一种用于深度信念网络在线训练和评估的自旋电子神经形态可重构阵列

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/ICRC.2018.8638604

Ramtin Zand, R. Demara

{"title":"SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks","authors":"Ramtin Zand, R. Demara","doi":"10.1109/ICRC.2018.8638604","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638604","url":null,"abstract":"In this paper, a spintronic neuromorphic reconfigurable Array (SNRA)is developed to fuse together power-efficient probabilistic and in-field programmable deterministic computing during both training and evaluation phases of restricted Boltzmann machines (RBMs). First, probabilistic spin logic devices are used to develop an RBM realization which is adapted to construct deep belief networks (DBNs)having one to three hidden layers of size 10 to 800 neurons each. Second, we design a hardware implementation for the contrastive divergence (CD)algorithm using a four-state finite state machine capable of unsupervised training in N+3 clocks where N denotes the number of neurons in each RBM. The functionality of our proposed CD hardware implementation is validated using ModelSim simulations. We synthesize the developed Verilog HDL implementation of our proposed test/train control circuitry for various DBN topologies where the maximal RBM dimensions yield resource utilization ranging from 51 to 2,421 lookup tables (LUTs). Next, we leverage spin Hall effect (SHE)-magnetic tunnel junction (MTJ)based non-volatile LUTs circuits as an alternative for static random access memory (SRAM)-based LUTs storing the deterministic logic configuration to form a reconfigurable fabric. Finally, we compare the performance of our proposed SNRA with SRAM-based configurable fabrics focusing on the area and power consumption induced by the LUTs used to implement both CD and evaluation modes. The results obtained indicate more than 80% reduction in combined dynamic and static power dissipation, while achieving at least 50% reduction in device count.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip 三维芯片中非冯诺依曼累积加速器的合并网络

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/ICRC.2018.8638619

Anirudh Jain, S. Srikanth, E. Debenedictis, T. Krishna

引用次数: 4

An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS 具有可编程电阻突触的28纳米CMOS振荡神经网络

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/ICRC.2018.8638600

T. C. Jackson, S. Pagliarini, L. Pileggi

引用次数: 26

ICRC 2018 Committees 红十字国际委员会2018委员会

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/icrc.2018.8638620

引用次数: 0

Parallel Quantum Computing Emulation 并行量子计算仿真

2018 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2018-11-01 DOI: 10.1109/ICRC.2018.8638597

B. Cour, S. Lanham, Corey I. Ostrove

{"title":"Parallel Quantum Computing Emulation","authors":"B. Cour, S. Lanham, Corey I. Ostrove","doi":"10.1109/ICRC.2018.8638597","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638597","url":null,"abstract":"Quantum computers provide a fundamentally new computing paradigm that promises to revolutionize our ability to solve broad classes of problems. Surprisingly, the basic mathematical structures of gate-based quantum computing, such as unitary operations on a finite-dimensional Hilbert space, are not unique to quantum systems but may be found in certain classical systems as well. Previously, it has been shown that one can represent an arbitrary multi-qubit quantum state in terms of classical analog signals using nested quadrature amplitude modulated signals. Furthermore, using digitally controlled analog electronics one may manipulate these signals to perform quantum gate operations and thereby execute quantum algorithms. The computational capacity of a single signal is, however, limited by the required bandwidth, which scales exponentially with the number of qubits when represented using frequency-based encoding. To overcome this limitation, we introduce a method to extend this approach to multiple parallel signals. Doing so allows a larger quantum state to be emulated with the same gate time required for processing frequency-encoded signals. In the proposed representation, each doubling of the number of signals corresponds to an additional qubit in the spatial domain. Single quit gate operations are similarly extended so as to operate on qubits represented using either frequency-based or spatial encoding schemes. Furthermore, we describe a method to perform gate operations between pairs of qubits represented using frequency or spatial encoding or between frequency-based and spatially encoded qubits. Finally, we describe how this approach may be extended to represent qubits in the time domain as well.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134213114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5