Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics

Optical circuits constructed using nanophotonic logic gates have attracted significant attention due to its ultra low-latency operation. This paper first introduces conventional optical logic circuits and their issues when the number of inputs is large. Then, we propose a method of minimizing the latency of large fan-in optical logic circuits using a multi-level optimization method. The proposed optimization method reduces not only the delay but also the attenuation of light involved in the circuits. Experimental results obtained targeting a 1024-bit pattern matching circuit show that the circuit optimized with our method is 1.72 times faster than the traditional optical circuit composed of the optical logic gates connected in series, and it is 3.40 times faster than the CMOS 32 nm circuit.