2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)最新文献_第2页

Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs 嵌入式gpu上汽车环境地图表示的建模、编程和性能分析

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748257

Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, J. Teich

{"title":"Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs","authors":"Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, J. Teich","doi":"10.1109/HLDVT.2016.7748257","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748257","url":null,"abstract":"Future Advanced Driver Assistance Systems (ADAS) require the continuous computation of detailed maps of the vehicle's environment. Due to the high demand of accuracy and the enormous amount of data to be fused and processed, common architectures used today, like single-core processors in automotive Electronic Control Units (ECUs), do not provide enough computing power. Here, emerging embedded multi-core architectures are appealing such as embedded Graphics Processing Units (GPUs). In this paper, we (a) identify and analyze common subalgorithms of ADAS algorithms for computing environment maps, such as interval maps, for suitability to be parallelized and run on embedded GPUs. From this analysis, (b) performance models are derived on achievable speedups with respect to sequential single-core CPU implementations. (c) As a third contribution of this paper, these performance models are validated by presenting and comparing a novel parallelized interval map GPU implementation against a parallel occupancy grid map implementation. For both types of environment maps, implementations on an Nvidia Tegra K1 prototype are compared to verify the correctness of the introduced performance models. Finally, the achievable speedups with respect to a single-core CPU solution are reported. These range from 3x to 275x for interval and grid map computations.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132808318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Accelerating assertion assessment using GPUs 使用gpu加速断言评估

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748249

J. G. Tong, M. Boule, Z. Zilic

引用次数: 0

Specification by existing design plus use-cases 现有设计加上用例的规格说明

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748253

Yusuke Kimura, M. Fujita

引用次数: 0

Fault injection ecosystem for assisted safety validation of automotive systems 辅助汽车系统安全验证的故障注入生态系统

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748256

Sebastian Reiter, A. Viehl, O. Bringmann, W. Rosenstiel

{"title":"Fault injection ecosystem for assisted safety validation of automotive systems","authors":"Sebastian Reiter, A. Viehl, O. Bringmann, W. Rosenstiel","doi":"10.1109/HLDVT.2016.7748256","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748256","url":null,"abstract":"The ever-increasing number of safety-related, complex, interconnected electronic systems results in new challenges. We propose a comprehensive fault injection ecosystem applicable along the design process to cope with these challenges. Simulation models are extended with fault injectors and used to assess the effects of faults. Our approach solves challenges specific to abstract system models and the reuse of existing simulation models. The proposed ecosystem consists of a system simulation infrastructure, a fault specification with dynamic fault injection, a fault effect classification and a graphical user interface. The simulation infrastructure enables the reuse and variation of simulation models and supports design space explorations. Our fault specification enables the specification and simulation of faults at different abstraction levels, especially at the abstract system level. The minimal invasive fault injection approach reduces the manual overhead when using existing simulation models and supports models of different abstraction levels. A failure classification extends the traditional verification methods. A graphical user interface simplifies the application and automatic code generation reduces the manual effort. The analysis of a driver assistance system demonstrates the usage of the proposed ecosystem.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117258491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats 基于TDML和VCD文件格式的可合成SVA协议校验器生成方法

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748248

Mohamed O. Kayed, Mohamed Abdelsalam, R. Guindi

引用次数: 1

Design space exploration for deterministic ethernet-based architecture of automotive systems 基于确定性网络的汽车系统体系结构设计空间探索

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748255

Prachi Joshi, G. VedahariNarasimhan, Haibo Zeng, S. Shukla, Chung-Wei Lin, Huafeng Yu

{"title":"Design space exploration for deterministic ethernet-based architecture of automotive systems","authors":"Prachi Joshi, G. VedahariNarasimhan, Haibo Zeng, S. Shukla, Chung-Wei Lin, Huafeng Yu","doi":"10.1109/HLDVT.2016.7748255","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748255","url":null,"abstract":"Time Triggered Ethernet (TTE) is a time-triggered network technology with large bandwidth and services for deterministic, safety-relevant communication. Hence, it has gained increasing attention from domains such as aerospace, automotive and industrial applications. In this work, we aim to solve the problem of task mapping and communication scheduling in automotive design. The system model is a dataflow task communication model mapped to a target architecture based on TIE. The design variables are the mapping of tasks onto the end systems in the architecture and the scheduling of all frames. The constraints include the schedulability of tasks and signals, as well as the latency constraints of the critical paths as specified by the designer. It can be shown that the problem is NP· hard. Therefore, we develop a heuristic to solve this problem. The heuristic contains four steps and all of them (except scheduling) are formulated using Integer Linear Programming (ILP). We present experimental results on an industrial benchmark and two synthetic benchmarks which show the efficiency and scalability of our approach.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123291786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Formal modeling of biological systems 生物系统的形式化建模

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748273

Qinsi Wang, E. Clarke

引用次数: 3

Cross-layer resilience: are high-level techniques always better? 跨层弹性:高级技术总是更好吗?

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748258

J. Abraham

引用次数: 1

Word-level traversal of finite state machines using algebraic geometry 使用代数几何的有限状态机的字级遍历

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748268

Xiaojun Sun, P. Kalla, Florian Enescu

引用次数: 7

Estimation of formal verification cost using regression machine learning 用回归机器学习估计形式验证代价

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748265

Eman El Mandouh, A. Wassal

{"title":"Estimation of formal verification cost using regression machine learning","authors":"Eman El Mandouh, A. Wassal","doi":"10.1109/HLDVT.2016.7748265","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748265","url":null,"abstract":"Formal Verification is a computationally expensive step in the verification of today's complex hardware designs. Effective results can be obtained from formal runs by planning ahead the effort and cost that are required for them. Additionally estimating in-advance the expected formal's complexity promotes a lot of potential tricks and clever setup techniques to overcome the initial push-button capacity limitation of the formal verifies and improve their capabilities to handle designs with higher complexity. This paper illustrates the application of regression machine learning (ML) techniques to build an estimation model for the cost of formal verification. Up to 10,000 formal verification runs on RTL designs with good varieties of design/properties attributes are used to learn the relationship between HW designs and the final formal cost in terms of formal run time. We demonstrate the use of Ridge-Regression to decide on the bias-variance trade-off during the regression-model design step as well as the application of Lasso-Regression for the feature selection phase. Finally a comparison between the proposed multiple linear regression approach and another non-parametric K-nearest neighbors kernel based regression technique is done to conclude on the presented work. Our results indicate how the proposed model managed to estimate with reasonable error ratio the expected formal verification effort for new-to-verify HW designs.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129075497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4