{"title":"Accelerating assertion assessment using GPUs","authors":"J. G. Tong, M. Boule, Z. Zilic","doi":"10.1109/HLDVT.2016.7748249","DOIUrl":null,"url":null,"abstract":"In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine an essential question in ABV: are the assertions effective at identifying design errors? Exploiting multiple parallelism factors, we show notable improvements in accelerating the simulations procedures that help to answer this fundamental question.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HLDVT.2016.7748249","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine an essential question in ABV: are the assertions effective at identifying design errors? Exploiting multiple parallelism factors, we show notable improvements in accelerating the simulations procedures that help to answer this fundamental question.