2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)最新文献

Formal semantics of behavior specifications in the architecture analysis and design language standard 体系结构分析和设计语言标准中行为规范的形式化语义

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-07 DOI: 10.1109/HLDVT.2016.7748252

L. Besnard, T. Gautier, Clément Guy, P. Guernic, J. Talpin, Brian R. Larson, Etienne Borde

引用次数: 7

SyQUAL: a platform for qualitative modelling and simulation of biological systems SyQUAL:一个生物系统定性建模和模拟的平台

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748270

Rosario Distefano, N. Goncharenko, F. Fummi, R. Giugno, Gary D Bader, N. Bombieri

{"title":"SyQUAL: a platform for qualitative modelling and simulation of biological systems","authors":"Rosario Distefano, N. Goncharenko, F. Fummi, R. Giugno, Gary D Bader, N. Bombieri","doi":"10.1109/HLDVT.2016.7748270","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748270","url":null,"abstract":"Qualitative modelling in systems biology is increasingly adopted as it allows predicting important properties of biological systems even when quantitative information of such systems are unknown. Even though different tools for qualitative modelling have been recently proposed, their lack of automatism and their unstructured simulation core limit their applicability to non-complex biological networks. This paper presents SyQUAL, a platform for qualitative modelling and simulation of biological systems. It consists of two main layers: a Web-based framework that allows users to (i) import models described in the standard Systems Biology Markup Language (SBML), (ii) easily define properties to observe, and (iii) run simulations by hiding the underlying layer, that is, a SystemC-based core simulator that allows simulating the systems through a discrete event-based model of computation at different levels of details. The paper shows how SyQUAL has been applied to identify the attractors and to analyse the system robustness/sensitivity under perturbations of the Colitis-associated Colon Cancer (CAC) network.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"29 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126158987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hardware-in-the-loop model-less diagnostic test generation 硬件在环无模型诊断测试生成

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748266

Sarmad Tanwir, M. Hsiao, L. Lingappan

{"title":"Hardware-in-the-loop model-less diagnostic test generation","authors":"Sarmad Tanwir, M. Hsiao, L. Lingappan","doi":"10.1109/HLDVT.2016.7748266","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748266","url":null,"abstract":"Iterative scan diagnosis is often needed for both the first silicon and the hard-to-diagnose chips. The chips in question are extracted from wafers and re-tested on a debug platform to arrive at a reasonable number of probable defect candidates that can be physically analyzed. This requires a large setup time and multiple iterations of deterministic diagnostic test pattern generation and application. In every iteration, offline software tools are used to diagnose observed failures and generate the needed new patterns to prune the list of defect candidates. In this paper, we propose an online approach for generating additional diagnostic patterns for the hard-to-diagnose chips without moving them to the debug platform. We generate these patterns directly on the tester through a fault model independent hardware-in-the-loop evolutionary algorithm. This algorithm is guided by a lightweight fitness metric that is solely based on the mismatches observed by applying the newly generated patterns to a pair of circuits consisting of a known good die and the chip being diagnosed. We evaluated our technique by comparing our results against a state-of-the-art commercial diagnostic pattern generation tool. Using our generated patterns, we were able to match the diagnosis quality of the commercial tool, while incurring significantly less runtime than the commercial tool on average. Our technique also eliminates the setup and other overhead costs of offline iterative diagnosis, which amounts to additional time savings.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121649961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Log2model: inferring behavioral models from log data Log2model:从日志数据推断行为模型

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748251

K. S. Luckow, C. Pasareanu

引用次数: 3

Deciphering cancer biology using boolean methods 用布尔方法解读癌症生物学

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748269

Subarna Sinha, D. Dill

引用次数: 0

Dynamic service synthesis and switching for medical IoT and ambient assisted living 医疗物联网和环境辅助生活的动态服务合成和切换

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748259

Daniel Yunge, Sangyoung Park, Philipp H. Kindt, G. Pravadelli, S. Chakraborty

{"title":"Dynamic service synthesis and switching for medical IoT and ambient assisted living","authors":"Daniel Yunge, Sangyoung Park, Philipp H. Kindt, G. Pravadelli, S. Chakraborty","doi":"10.1109/HLDVT.2016.7748259","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748259","url":null,"abstract":"In the Internet of Things (IoT), our surrounding will include a large variety of devices from different manufacturers. One of its promising branches, the medical IoT, will also be accompanied by heterogeneous smart-home infrastructures. However, the efficacy of a medical IoT application will depend on how well the surrounding smart devices collaborate with it to serve the individual needs of the users. Pre-programmed solutions lack flexibility to adapt to each need and environment, and fail to make full use of the capabilities of a set of smart devices. In this paper, we propose a concept based on the flexible and user-friendly synthesis and switching of services for medical IoT applications. The crux of the concept is to provide a methodology in which non-experts can dynamically define services based on their needs. We describe a potential scenario, discuss the associated challenges, and present preliminary results on the feasibility of this approach. Particularly, we focus on design aspects for realizing the concept and propose the use of interpreters on the smart devices as alternative solution. We show that such an approach is feasible in terms of implementation and energy consumption while still maintaining the full flexibility of the service synthesis.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130370934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A segment-aware multi-core scheduler for system C PDES 用于系统C PDES的段感知多核调度器

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748262

Guantao Liu, T. Schmidt, R. Dömer

引用次数: 4

Design centric modeling of digital hardware 以设计为中心的数字硬件建模

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748254

Johannes Schreiner, Rainer Findenig, W. Ecker

{"title":"Design centric modeling of digital hardware","authors":"Johannes Schreiner, Rainer Findenig, W. Ecker","doi":"10.1109/HLDVT.2016.7748254","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748254","url":null,"abstract":"Today's dominant RTL languages, VHDL and (System) Verilog, were designed as description and simulation languages. Therefore, they have a clearly defined - but not in all cases deterministic - simulation algorithm as backbone of the language definition. Both languages have been adopted as RTL design languages but still impose a lot of simulation/synthesis mismatches. As a further disadvantage, considerable overhead can be needed to code well-known hardware patterns such as FSMs. Finally, the simulation algorithm prevents efficient simulation (e.g. two-state or cycle-based simulation) as well as advanced model analysis (e.g. X-propagation) or fosters an execution that is not in sync with the language definition. Therefore, we developed a design centric modeling approach that allows a clear specification of the design intent and provides freedom for various target HDLs and modeling styles. Since our approach is specified without underlying simulation semantics, we provide a formal definition considering only certain points in simulation traces, thus enabling various ways for simulation. To avoid syntactic sugar, we selected a metamodeling based approach, which we use as part of a modeldriven generation-focused design approach.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123977995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Automatically adjusting system level designs after RTL/gate-level ECO RTL/门级ECO后自动调整系统电平设计

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748263

Qinhao Wang, Yusuke Kimura, M. Fujita

{"title":"Automatically adjusting system level designs after RTL/gate-level ECO","authors":"Qinhao Wang, Yusuke Kimura, M. Fujita","doi":"10.1109/HLDVT.2016.7748263","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748263","url":null,"abstract":"In this paper we discuss techniques by which system level designs in C can be automatically modified or refined to be equivalent to given implementation designs in RTL/netlists, assuming that the numbers of statements in C to be changed are small, e,g., one to several statements. This can correspond to the cases when RTL/gate-level ECO (Engineering Change Order) happens, as under ECO usually small portions of designs or small functionalities are changed. In the proposed method, templates are generated from the original C descriptions by replacing a set of statements with parameterized and programmable statements having symbolic variables that represent program variables, constants, operators and others. Then the problem to refine templates so that the resulting C descriptions become equivalent to the implementation designs is formulated as a QBF (Quantified Boolean Formula) problem. The QBF problem is solved by repeatedly applying SAT solvers in incremental ways without any formal analysis on the implementation designs. Implementation designs are just simulated by a number of times. This process also generates a set of test patterns by which the equivalence between the C descriptions with refined templates and the implementations can be 100% guaranteed as long as the templates can capture the behaviors of the implementation designs. We show preliminary experimental results which show usefulness of the proposed approach.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116968118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Control-flow guided clause generation for property directed reachability 为属性定向可达性生成控制流引导子句

2016 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2016-10-01 DOI: 10.1109/HLDVT.2016.7748250

Xian Li, K. Schneider

{"title":"Control-flow guided clause generation for property directed reachability","authors":"Xian Li, K. Schneider","doi":"10.1109/HLDVT.2016.7748250","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748250","url":null,"abstract":"Property directed reachability (PDR) has been introduced as a very efficient verification method for synchronous hardware circuits which is based on induction rather than fixpoint computation. The method incrementally refines a sequence of clause sets that over-approximate the states that are reachable in finitely many steps. Even being valid, safety properties may not be provable by induction due to so-called counterexamples to induction (CTIs) that result from the over-approximation of the reachable states. Crucial steps of the PDR method therefore consist of (1) deciding about the reachability of states derived from counterexamples, and (2) generalizing them to clauses that cover as many unreachable states as possible that are then excluded from consideration by adding the generated clause to the reachable state approximation sequence. In this paper, we describe a refinement of the PDR method for synchronous programs that makes effective use of the distinction between the control- and dataflow of synchronous programs. If a CTI candidate is found, we reduce it to its control-flow part and check whether the obtained control-flow states are unreachable in the corresponding extended finite state machine of the program. If so, we can immediately exclude all these states by adding the negation of the control-flow part as a new clause to the current reachable state approximations; otherwise, the usual steps of the PDR method are applied. This additional step in the PDR method is not expensive, and can significantly increase the performance of PDR.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115096170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4