Hardware-in-the-loop model-less diagnostic test generation

Abstract

Iterative scan diagnosis is often needed for both the first silicon and the hard-to-diagnose chips. The chips in question are extracted from wafers and re-tested on a debug platform to arrive at a reasonable number of probable defect candidates that can be physically analyzed. This requires a large setup time and multiple iterations of deterministic diagnostic test pattern generation and application. In every iteration, offline software tools are used to diagnose observed failures and generate the needed new patterns to prune the list of defect candidates. In this paper, we propose an online approach for generating additional diagnostic patterns for the hard-to-diagnose chips without moving them to the debug platform. We generate these patterns directly on the tester through a fault model independent hardware-in-the-loop evolutionary algorithm. This algorithm is guided by a lightweight fitness metric that is solely based on the mismatches observed by applying the newly generated patterns to a pair of circuits consisting of a known good die and the chip being diagnosed. We evaluated our technique by comparing our results against a state-of-the-art commercial diagnostic pattern generation tool. Using our generated patterns, we were able to match the diagnosis quality of the commercial tool, while incurring significantly less runtime than the commercial tool on average. Our technique also eliminates the setup and other overhead costs of offline iterative diagnosis, which amounts to additional time savings.