Word-level traversal of finite state machines using algebraic geometry

Reachability analysis is a tool for formal equivalence and model checking of sequential circuits. Conventional techniques are mostly bit-level, in that the reachable states, transition relations and property predicates are all represented using Boolean variables and functions. The problem suffers from exponential space and time complexities; therefore, some form of abstraction is desirable. This paper introduces a new concept of implicit state enumeration of finite state machines (FSMs) performed at the word-level. Using algebraic geometry, we show that the state-space of a sequential circuit can be encoded, canonically, as the zeros of a word-level polynomial F (S) over the Galois field F2k, where S = {s0, ..., sk-1} is the word-level representation of a k-bit state register. Subsequently, concepts of elimination ideals and Grobner bases can be employed for FSM traversal. The paper describes the complete theory of word-level FSM traversal and demonstrates the feasibility of the approach with experiments over a set of sequential circuit benchmarks.