Cross-layer resilience: are high-level techniques always better?

Computers are pervasive in society because advances in integrated circuit (IC) technology have enabled increased performance and reduced costs. In many critical applications, the ICs need to continue to operate correctly in spite of manufacturing defects, as well as failures during operation due to wearout or external disturbances. Although thorough testing of the ICs is part of the manufacturing cycle, some defects may escape the screening; during operation, interconnects may wear out due to electromigration and transistors could degrade (for example, due to negative bias temperature instability (NBTI)). This could result in incorrect results produced by the circuits. Errors can also be produced during operation due to crosstalk, voltage droops (which lead to increased delays in critical paths), single event upsets due to external radiation, etc. Therefore, systems comprising the ICs need to be designed to be resilient, i.e., detect and correct errors due to failures.