2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)最新文献_第2页

Comparison of machine learning algorithms to predict daily water consumptions 预测日常用水量的机器学习算法比较

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9498103

Aida Boudhaouia, P. Wira

{"title":"Comparison of machine learning algorithms to predict daily water consumptions","authors":"Aida Boudhaouia, P. Wira","doi":"10.1109/DTS52014.2021.9498103","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498103","url":null,"abstract":"This paper focuses on a comparison of machine learning algorithms for predicting the cumulative daily water consumption. The data are collected from an internet-based platform that provides usable data. A pre-processing has been designed for checking the integrity of data, i.e., detecting missing data and abnormal consumptions. In order to optimize the water uses in distribution networks, monitoring and forecasting consumption are good solutions. Five models, namely the Polynomial Regression (PR), Nonlinear AutoRegressive (NAR), Support Vector Regression (SVR), MultiLayer Perceptron (MLP) and Long Short-Term Memory (LSTM) are designed and compared to find the most accurate solution to forecast daily water consumption. The performance of these models is based on the Root Mean Square Error (RMSE) calculated from desired values. The water consumption for the next five days is predicted with no prior information but only centralized past measurements. Results show a predicting precision with NAR of about 5 and 23 l/day in respectively domestic and industrial installations where up to 1500 and 2700 l/day can be used.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117038631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Novel Capacitive MEMS Logic Gates For Logic Circuits and Systems 用于逻辑电路和系统的新型电容式MEMS逻辑门

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9498255

H. Samaali, Mohamed Amin Ben Hassena, F. Najar

引用次数: 0

Analysis and Detection of Errors in KECCAK Hardware Implementation KECCAK硬件实现中的错误分析与检测

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9497889

H. Mestiri, I. Barraj, Mohsen Machhout

{"title":"Analysis and Detection of Errors in KECCAK Hardware Implementation","authors":"H. Mestiri, I. Barraj, Mohsen Machhout","doi":"10.1109/DTS52014.2021.9497889","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9497889","url":null,"abstract":"The third family Secure Hash Algorithm cryptographic function, named KECCAK, is implemented in cryptographic circuits to assure high security level to any system which necessitates hashing as the generation of random numbers and the data integrity checking. One of the most efficient physical attacks against KECCAK hardware implementation is the fault attacks which can extract the secret data. Until today, a few KECCAK fault detection schemes against the fault attacks have been presented. In this paper, in order to provide a high level of security against fault attacks, we perform a detailed fault analysis to estimate the impact of fault attacks against the KECCAK implementation. We then propose an efficient error detection scheme based on the KECCAK architecture modification. For this reason, the round of KECCAK is divided into two half rounds and a KECCAK pipeline register is implemented between them. The proposed scheme is independent of the method the KECCAK is implemented. Thus, it can be applied to both the pipeline and iterative architectures.To evaluate the KECCAK detection scheme robustness against faults injection attacks, we perform fault injection attacks and we determined the fault detection capability; it is about 99.997%. We have modeled the KECCAK detection scheme using the VHDL hardware language and through hardware FPGA implementation, the FPGA results demonstrate that our scheme can efficiently secure the KECCAK implementation against fault attacks. It can be simply implemented with low complexity. In addition, the FPGA implementation performances prove the low slice area overhead and the high working frequency for the proposed KECCAK detection scheme.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116928461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Novel Robust Blind AES/LWT+DCT+SVD-Based Crypto-Watermarking schema for DICOM Images Security 一种基于AES/LWT+DCT+ svd的DICOM图像鲁棒盲加密水印方案

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9497916

Mohamed Boussif, Oussema Bouferas, Noureddine Aloui, A. Cherif

引用次数: 4

Testing Inter-Chiplet Communication Interconnects in a Disaggregated SoC Design 在分解SoC设计中测试片间通信互连

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9498132

S. Abdennadher

引用次数: 2

Electrothermal RRAM Crossbar Improvement with 3-D CRS and 1D1R-1R1D Architectures 基于3-D CRS和1D1R-1R1D架构的电热RRAM横条改进

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9498259

K. Lahbacha, H. Belgacem, W. Dghais, F. Zayer, A. Maffucci

引用次数: 0

Characterization of GNRFET Devices for Applications towards 5G Communication 面向5G通信应用的GNRFET器件的特性

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9498056

M. Rahmani, Mounica Patnala, T. Ytterdal, M. Rizkalla

{"title":"Characterization of GNRFET Devices for Applications towards 5G Communication","authors":"M. Rahmani, Mounica Patnala, T. Ytterdal, M. Rizkalla","doi":"10.1109/DTS52014.2021.9498056","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498056","url":null,"abstract":"The fifth generation (5G) wireless technology will provide the nation’s future telecommunications network, featuring higher bandwidth and data rates with lower delay and power consumption. This shift facilitates the ultra-level of integration, for systems loaded with embedded sensors that are enabled by this technology. A few challenges remain regarding the standards to proper interfacing, security for cellular based services, and ability of portable devices to be employed in this technology. These challenges include high-speed amplifiers and signal processors. Millimeter wave communications with frequencies above 10 GHz for mobile networks may be required to meet the propagation quality demands of this technology. This paper proposes the Graphene Nano Ribbon Field Effect Transistor (GNRFET) device as a potential candidate that fits well in this technology, featuring high frequency amplifiers and high switching speed in digital circuits with ultra-low power consumption. These advantages may be attributed to the high mobility and mean free path of the device, leading to major ballistic carrier transport. The simulation was conducted at a switching speed in the order of 10GHz and 0.7V supply. The device was also employed for high frequency amplifiers, achieving as much as 5.1 THz gain bandwidth product (70GHz at a gain of 75), with very clean output signals. Near 115 dBs attenuation losses for harmonics was determined within the operating bandwidth. This paper details the device model, circuit design, and power consumption, suitable for the 5-G communication system. The nanoscale size of the device provides the ultra-level of integration, incorporating the embedded and IoT devices supporting this technology.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124680854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Development of graphene oxide-based fluorescent sensing nanoplatform for microRNA-10b detection 基于氧化石墨烯的微rna -10b荧光传感纳米平台的研制

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9497926

Maroua Moslah, K. Djebbi, C. Tlili, C. Dridi, Deqiang Wang

引用次数: 0

HBONext: HBONet with Flipped Inverted Residual HBONext:带反转残差的HBONet

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9498121

S. Joshi, M. El-Sharkawy

{"title":"HBONext: HBONet with Flipped Inverted Residual","authors":"S. Joshi, M. El-Sharkawy","doi":"10.1109/DTS52014.2021.9498121","DOIUrl":"https://doi.org/10.1109/DTS52014.2021.9498121","url":null,"abstract":"The top-performing deep CNN (DCNN) architectures are presented every year based on their compatibility and performance ability on the embedded edge applications, significantly for image classification. There are many obstacles in making these neural network architectures hardware friendly due to the limited memory, lesser computational resources, and the energy requirements of these devices. The addition of Bottleneck modules has further helped this classification problem, which explores the channel interdependencies, using either depthwise or groupwise convolutional features. The classical inverted residual block, a well-known design methodology, has now gained more attention due to its growing popularity in portable applications. This paper presents a mutated version of Harmonious Bottlenecks (DHbneck) with a Flipped version of Inverted Residual (FIR), which outperforms the existing HBONet architecture by giving the best accuracy value and the miniaturized model size. This FIR block performs identity mapping and spatial transformation at its higher dimensions, unlike the existing concept of inverted residual. The devised architecture is tested and validated using CIFAR-10 public dataset. The baseline HBONet architecture has an accuracy of 80.97% when tested on CIFAR-10 dataset and the model’s size is 22 MB. In contrast, the proposed architecture HBONext has an improved validation accuracy of 88.30% with a model reduction to a size of 7.66 MB.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124194114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Intra-Prediction Rate-Distortion of Next-Generation VVC and HEVC Encoders 下一代VVC和HEVC编码器的预测内速率失真

2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Pub Date : 2021-06-07 DOI: 10.1109/DTS52014.2021.9498186

Amira Mehri, N. Belhadj, David Parello, A. Mtibaa

引用次数: 0