Testing Inter-Chiplet Communication Interconnects in a Disaggregated SoC Design

Abstract

The integration of High-bandwidth memory (HBM), is essentially one of the first proof points of in-package integration of heterogeneous silicon that gained steam using advanced packaging. Intel has demonstrated heterogenous integration through chiplet architecture and disaggregation in multiple products and different market segments. With the chiplet model gaining momentum as an alternative to developing monolithic SoC designs, which are becoming more complex and expensive at each node, Test is one of the major enablers of a wider adoption and development of chiplet ecosystem. Die-to-die (D2D) interconnect between chiplets raises complex test challenges, which are driving new standards and DfT approaches to advanced-package testing. This paper addresses these test challenges and emerging solutions for testing D2D interconnect in a disaggregated SoC design.