{"title":"Design of an interconnection network using VLSI photonics and free-space optical technologies","authors":"R. Chamberlain, M. Franklin","doi":"10.1109/PI.1999.806395","DOIUrl":"https://doi.org/10.1109/PI.1999.806395","url":null,"abstract":"This paper presents the design and initial analysis of an optically interconnected multiprocessor based on the use of VCSELs (Vertical Cavity Surface Emitting Lasers) and free-space optical interconnects. The design is oriented to applications where the performance is bandwidth limited in conventional multiprocessors. The processor interconnection network is based on a physical ring topology which is logically configured as a multiring. Two alternative communications protocols are presented and the performance properties associated with a packet-based Go-Back-N protocol are discussed. Relationships between bit error rate and performance are provided.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130081930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Nishimura, T. Kudoh, H. Nishi, K. Harasawa, N. Matsudaira, S. Akutsu, K. Tasyo, H. Amano
{"title":"A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections","authors":"S. Nishimura, T. Kudoh, H. Nishi, K. Harasawa, N. Matsudaira, S. Akutsu, K. Tasyo, H. Amano","doi":"10.1109/PI.1999.806389","DOIUrl":"https://doi.org/10.1109/PI.1999.806389","url":null,"abstract":"A large throughput, low latency network switch (RHiNET-2/SW) has been developed for a distributed parallel computing system. This switch has a new architecture to support low latency \"zero-copy\" communication in multi-tasking environments. Eight pairs of 800-Mbit/s/spl times/12-channel optical interconnection modules and a CMOS ASIC switch are implemented on a compact circuit board. To achieve large-throughput (64 Gbit/s) and low-latency network performance, the SW-LSI has a customized high-speed LVDS I/O interface, and high-speed internal SRAM memory in a 784-pin-BGA one-chip package. Also, we have developed the device implementation technologies to overcome the electrical problems (crosstalk, skew, reflection and noise). These implementation technologies are applicable for switches used in other high-speed networks such as GSN, 4 Gbit/s Fiber Channel or 10 Gbit/s Ethernet.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121020398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated micro-optical assemblies for optical interconnects","authors":"M. Feldman, H. Han, J. Stack, J. Mathews","doi":"10.1109/PI.1999.806405","DOIUrl":"https://doi.org/10.1109/PI.1999.806405","url":null,"abstract":"Integrated micro-optical systems (IMOS) are integrated assemblies of multiple optical components that are made and assembled at the wafer level using semiconductor processing techniques. IMOS has been used to create 3-dimensional optical systems in a cost-effective highly manufacturable manner. Collimated lens arrays have been fabricated with experimental total round trip insertion loss of 1.5-2.0 dB per channel.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132297945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Feedback-based synchronization for QoS traffic in cluster computing","authors":"H. Song, A. Chien","doi":"10.1109/PI.1999.806413","DOIUrl":"https://doi.org/10.1109/PI.1999.806413","url":null,"abstract":"Many applications in cluster computing require performance predictability. One way to ensure that is to generate global schedules and execute the local portion of the schedules at each network interface. With a local clock at each network interface, it is essential that the clocks share a global notion of time. The task of maintaining a single notion of time is called the synchronization problem and this paper addresses it for cluster computing environments. To solve the synchronization problem, FM-QoS proposed a simple notion of synchronization called FBS (Feedback Based Synchronization) for a single switch network. For the generalization of FBS into any networks, this paper extends the basic notion of FBS to a theoretical framework: (1) to identify a set of network flow control signals for synchrony and formalize it in the form of a synchronizing schedule; and (2) to establish the skew analysis model which measures the synchronization precision. Based on the analysis, numerical results are obtained with flow control parameters of Myrinet-1280/SAN. At every observed point, the skew and a network bandwidth overhead of FBS are less than 1.7 /spl mu/s and 5%, respectively, which shows the usability of FBS. With the proposed framework of FBS, this paper concludes that FBS can be an attractive synchronization mechanism in cluster computing environments.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124699719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High speed parallel multi-chip interconnection with free space optics","authors":"Xuezhe Zheng, P. Marchand, D. Huang, S. Esener","doi":"10.1109/PI.1999.806390","DOIUrl":"https://doi.org/10.1109/PI.1999.806390","url":null,"abstract":"In this paper, a high-speed parallel data communication scheme is proposed for multi-chip interconnections. We present the proof of concept and feasibility demonstration of a practical module packaging approach where free-space optical interconnects can be seamlessly integrated on electronic Multi-Chip Modules (MCM) for intra MCM interconnects. Our system level packaging architecture is based on a modified folded 4-f imaging system that has been implemented using only off-the-shelf optics, conventional electronic packaging, as well as passive alignment and assembly techniques to yield a potentially low cost manufacturable packaging solution. The prototype system, as built, supports 48 independent FSOI channels using eight separate laser and detector chips, where each chip consists of a 1D array of 12 devices. All chips are assembled on a single ceramic substrate together with three silicon chips. Parallel opto-electronic free space interconnections have been demonstrated with link speeds of up to 200 MHz per channel. The system is compact at only 10 cubic inches, and scalable as it can easily accommodate additional chips as well as two-dimensional opto-electronic device arrays for increased interconnection density.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J.A. Martinez, S. Levitan, T. Kurzweg, E. N. Reiss, M. T. Shomsky, P. Marchand, D. Chiarulli
{"title":"Modeling free space optoelectronic interconnects","authors":"J.A. Martinez, S. Levitan, T. Kurzweg, E. N. Reiss, M. T. Shomsky, P. Marchand, D. Chiarulli","doi":"10.1109/PI.1999.806400","DOIUrl":"https://doi.org/10.1109/PI.1999.806400","url":null,"abstract":"This paper presents a system level optoelectronic CAD tool, Chatoyant, which has been developed to meet the needs of mixed technology systems designers. We introduce component models and analysis techniques that enable our tool to support optoelectronic interconnect system design. We demonstrate these results with the analysis of two optoelectronic interconnection systems: a multi-channel high-speed link and a 1/spl times/2 optical MEM interferometer switch.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133546153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On worst case analysis of permutation routing on data manipulators","authors":"E. Elmallah, Chin-Hung Lam","doi":"10.1109/PI.1999.806403","DOIUrl":"https://doi.org/10.1109/PI.1999.806403","url":null,"abstract":"This paper deals with the the following problem: given an N/spl times/N augmented data manipulator network and a permutation /spl pi/ between its N inputs and outputs, does there exist a polynomial time deterministic algorithm that decides whether /spl pi/ is admissible thorough the network? A number of backtrack search algorithms have been formalized in the literature to solve the problem. None of the published results, however, appear to settle the time complexity of the problem. The goal of this paper is to answer the question positively by showing an O(N/sup 1.695/) time bound for solving the problem. The running time is asymptotically optimal, and the given algorithm computes a setting of the switches whenever /spl pi/ is admissible.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117161706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. D. Kimura, J. R. Gilman, R. A. Livingston, K. Chan, R. Chamberlain
{"title":"Wireless data path for a mobile, modular computer system","authors":"T. D. Kimura, J. R. Gilman, R. A. Livingston, K. Chan, R. Chamberlain","doi":"10.1109/PI.1999.806409","DOIUrl":"https://doi.org/10.1109/PI.1999.806409","url":null,"abstract":"We present a comparison of two technologies for use in implementing a wireless data path. The target environment is a mobile, modular computer system that aims to improve the economics and productivity of users that currently use multiple PCs. An inductive power delivery subsystem is described, and both optical and capacitive data delivery subsystems are compared.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131633091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optical interconnects based on hybrid CMOS/VCSEL arrays","authors":"A. Krishnamoorthy, R. Rozier","doi":"10.1109/PI.1999.806392","DOIUrl":"https://doi.org/10.1109/PI.1999.806392","url":null,"abstract":"Summary form only given. The authors discuss the concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit. Before such a technology can be deployed on a large scale, several issues related to the scalability of the optoelectronic technology and its compatibility with deep sub-micron CMOS technologies must be addressed. In terms of the VCSELs, the challenge will be in producing arrays of VCSELs that can be attached to CMOS circuits with high yield, and be simultaneously operated at high speeds. In terms of the circuits, the challenges will be to continue to improve receiver sensitivity while reducing power dissipation and crosstalk. A final consideration is that of the systems integration, where the challenge will be to package systems that can efficiently transport large arrays of light beams to and from such chips.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129307915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. García, J. Cowan, G. Still, C. Madison, M. Bradley, K. Potter
{"title":"Future I/O","authors":"D. García, J. Cowan, G. Still, C. Madison, M. Bradley, K. Potter","doi":"10.1109/PI.1999.806417","DOIUrl":"https://doi.org/10.1109/PI.1999.806417","url":null,"abstract":"Future I/O provides a high-performance switched-fabric interconnect to enable both host-to-host and host-to-I/O node communication. Providing inherent redundancy characteristics, 1 GB/sec data rates and support for legacy IP, this architecture will satisfy bandwidth requirements for a number of applications for years to come. The architecture enables very low-cost implementations for adapter vendors and also scales to very high-end IPC and more complex data exchange scenarios. This will lead to use of this architecture throughout the computer industry.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129221822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}