Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)最新文献

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PAROLI(R)-a parallel optical link with 15 Gbit/s throughput in a 12-channel wide interconnection PAROLI(R)-在12通道宽互连中具有15gbit /s吞吐量的并行光链路
D. Kuhl, K. Drogemuller, J. Blank, M. Ehlert, T. Kraeker, J. Hohn, D. Klix, V. Plickert, L. Melchior, P. Hildebrandt, M. Heinemann, A. Beier, L. Leininger, H.-D. Wolf, T. Wipiejewski, R. Engel
{"title":"PAROLI(R)-a parallel optical link with 15 Gbit/s throughput in a 12-channel wide interconnection","authors":"D. Kuhl, K. Drogemuller, J. Blank, M. Ehlert, T. Kraeker, J. Hohn, D. Klix, V. Plickert, L. Melchior, P. Hildebrandt, M. Heinemann, A. Beier, L. Leininger, H.-D. Wolf, T. Wipiejewski, R. Engel","doi":"10.1109/PI.1999.806411","DOIUrl":"https://doi.org/10.1109/PI.1999.806411","url":null,"abstract":"A parallel optical link, PAROLI(R), with over 15 Gbit/s throughput for both asynchronous and synchronous data transmission is described. The link consists of discrete transmitter and receiver modules and a low skew cable system. The PAROLI(R) system operates with 12 optical channels at data rates of up to 1.25 Gbit/s per channel. The oxide-confined VCSEL array, the pin diode array and the ICs are designed to operate at 3.3 Volts. Methods of system performance evaluation by eye diagram analysis and BER scan techniques are discussed. Improvements of key component features are presented, pointing towards 2.5 Gbit/s transmission per optical channel in the near future.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127261297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A multi-layer-perceptron neural network hardware based on 3D massively parallel optoelectronic circuits 一种基于三维大规模并行光电电路的多层感知器神经网络硬件
K. D. Maier, C. Beckstein, Reinhard Blickhan, Werner Erhard, Dietmar Fey
{"title":"A multi-layer-perceptron neural network hardware based on 3D massively parallel optoelectronic circuits","authors":"K. D. Maier, C. Beckstein, Reinhard Blickhan, Werner Erhard, Dietmar Fey","doi":"10.1109/PI.1999.806397","DOIUrl":"https://doi.org/10.1109/PI.1999.806397","url":null,"abstract":"A digital neural network architecture is presented which is based on three-dimensional massively parallel optoelectronic circuits. A suitable optical interconnect system and the structure of the required electronic circuits is specified. For this system general formulas for the performance of such a neural network architecture are determined. A parameter study using current technological limitations and timing values from electronic implementation is carried out. Based on this analysis if is shown that this novel type of neuroarchitecture that is using 3D massively parallel optoelectronic circuits shows performance rates of up to one magnitude higher than systems using digital neurochips based on fully electronic implementation.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130753157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
3-D optical networks of directional couplers and Mach-Zehnder 定向耦合器和Mach-Zehnder的三维光网络
J. Giglmayr
{"title":"3-D optical networks of directional couplers and Mach-Zehnder","authors":"J. Giglmayr","doi":"10.1109/PI.1999.806415","DOIUrl":"https://doi.org/10.1109/PI.1999.806415","url":null,"abstract":"Principles of the proper design of intersection graphs (IGs) of 3-D networks of directional couplers (DCs) and Mach-Zehnder interferometers (MZIs) and their classification are presented. The IGs are described in graph theoretical terms as well as by the number of DCs and MZIs, respectively. Routing within the IGs (and in turn within the spatial switch) and future work is also discussed.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"abs/1602.05312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123842433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Matrix multiplication on the OTIS-Mesh optoelectronic computer OTIS-Mesh光电计算机上的矩阵乘法
Chih-Fang Wang, S. Sahni
{"title":"Matrix multiplication on the OTIS-Mesh optoelectronic computer","authors":"Chih-Fang Wang, S. Sahni","doi":"10.1109/PI.1999.806404","DOIUrl":"https://doi.org/10.1109/PI.1999.806404","url":null,"abstract":"We develop algorithms to multiply two vectors, a vector and a matrix, and two matrices on an OTIS-Mesh optoelectronic computer. Two mappings, group row and group sub-mesh of a matrix onto an OTIS-Mesh are considered and the relative merits of each compared.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125104886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 84
Parallel optical interconnects for high performance printed circuit boards 用于高性能印刷电路板的并行光学互连
E. Griese
{"title":"Parallel optical interconnects for high performance printed circuit boards","authors":"E. Griese","doi":"10.1109/PI.1999.806410","DOIUrl":"https://doi.org/10.1109/PI.1999.806410","url":null,"abstract":"A novel and innovative interconnection technology for printed circuit board application is presented which is able to meet the high performance requirements of future electronic equipment while at the same time improving the electromagnetic compatibility (EMC) significantly. This technology will have a far-reaching compatibility with the existing printed circuit board technology, which means that the design and manufacturing processes of the electrical part do not need significant modifications. After a short description of the most important basic technologies and results for its realization, the paper focuses on the design and modeling of parallel electrical/optical interconnection systems. Transient analysis is addressed in order to provide an efficient analysis methodology as well as algorithms for timing and signal integrity prediction necessary for designing and manufacturing high-speed electronic systems of high quality. The developed overall modeling strategy is explained and first available results are presented. Besides a time domain transmission line model for parallel optical multimode structures considering delay, losses, dispersion, and crosstalk the corresponding modeling approaches for laser- and photo-diodes are presented.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132400468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Ultra-fast low-latent superconductor packet switching networks for petaflops computing 用于千万亿次浮点运算的超高速低潜超导分组交换网络
D. Zinoviev, L. Wittie
{"title":"Ultra-fast low-latent superconductor packet switching networks for petaflops computing","authors":"D. Zinoviev, L. Wittie","doi":"10.1109/PI.1999.806396","DOIUrl":"https://doi.org/10.1109/PI.1999.806396","url":null,"abstract":"This work is a part of a project to design a petaflops-scale computer using a hybrid technology multi-threaded architecture (HTMT). In the core of the superconductor part of the HTMT system there should be a high-bandwidth low-latency superconductor RSFQ switching network (CNET) connecting 4,096 computing modules with each other and with room-temperature semiconductor components. We present a study of the CNET for two alternative architectures: banyan and pruned high-dimensional meshes. The results indicate that with the speed and space limitations accepted in the HTMT concept, CNET will be able to provide a cross-sectional bandwidth of about 3/5 packet per processor per network clock cycle (in the HTMT concept, 32 ps). We have designed a simple 2/spl times/2 internal switching node which can be used to construct more complex networks using either of the architectures, and experimentally demonstrated successful operation of a 2-bit-wide data path.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134362093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The PHOTOBUS smart pixel interconnection system for symmetric multiprocessing using workstation clusters PHOTOBUS智能像素互连系统,使用工作站集群进行对称多处理
P. Lukowicz
{"title":"The PHOTOBUS smart pixel interconnection system for symmetric multiprocessing using workstation clusters","authors":"P. Lukowicz","doi":"10.1109/PI.1999.806401","DOIUrl":"https://doi.org/10.1109/PI.1999.806401","url":null,"abstract":"This paper describes how a smart pixel/fibre ribbon interconnection system, PHOTOBUS, can be used to extend the symmetric multiprocessor architecture usually found in multiprocessor workstations to workstation clusters. This could significantly simplify the programming of such clusters, increase their efficiency for a wide range of applications, and provide a uniform programming model for multiprocessor workstations and workstation clusters. The paper describes the protocols necessary to correctly and efficiently implement a symmetric multi-processor using the PHOTOBUS interconnection. We also present the results of a simulation of the performance of such systems using the SPLASH-2 shared memory benchmarks. The simulation demonstrates that good efficiency can be achieved using currently feasible technology.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116115269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Disk write caching with an optical network 基于光网络的磁盘写缓存
E. V. Carrera, Ricardo Bianchini
{"title":"Disk write caching with an optical network","authors":"E. V. Carrera, Ricardo Bianchini","doi":"10.1109/PI.1999.806414","DOIUrl":"https://doi.org/10.1109/PI.1999.806414","url":null,"abstract":"In this paper we propose a simple extension to the optical network of a scalable multiprocessor that optimizes page swap-outs significantly. More specifically, we propose to extend the network with an optical ring that not only transfers swapped-out pages between the local memories and the disks of the multiprocessor but also acts as a system-wide write cache for these pages. This extended optical network has several performance benefits: it provides a staging area where swapped-out pages can reside until the disk is free; it increases the possibility of combining several writes to disk; and it acts as a victim cache for pages that are swapped out and subsequently accessed by the same or a different processor. In order to evaluate the extent to which these benefits affect performance, we use detailed execution-driven simulations of several out-of-core parallel applications running on an 8-node scalable multiprocessor. Our results demonstrate that our optical ring provides consistent performance improvements, coming mostly from faster page swap-outs and victim caching. Based on these results and on our parameter space study, our main conclusion is that our optical ring is highly efficient under several architectural assumptions and for most out-of-core parallel applications.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121895162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quantifying the impact of optical interconnect latency on the performance of optoelectronic FPGAs 量化光互连延迟对光电fpga性能的影响
J. Dambre, H. V. Van Marck, J. V. Van Campenhout
{"title":"Quantifying the impact of optical interconnect latency on the performance of optoelectronic FPGAs","authors":"J. Dambre, H. V. Van Marck, J. V. Van Campenhout","doi":"10.1109/PI.1999.806399","DOIUrl":"https://doi.org/10.1109/PI.1999.806399","url":null,"abstract":"In this paper, we address the possible advantages of using optoelectronic area-I/O to realize three-dimensional multi-FPGA architectures. Our approach is based on experimental determination of achievable clock rates when realizing synchronous designs. Our experiments indicate that three-dimensional optoelectronic multi-FPGA architectures exhibit higher performance than traditional two-dimensional electronic FPGAs, provided the optical link latency is sufficiently low. It turns out that with latencies of state of the art optical links the gains can be positive, in particular for large and complex designs.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121583945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
From HiPPI-800 to HiPPI-6400: A changing of the guard and gateway to the future 从HiPPI-800到HiPPI-6400:改变守卫和通往未来的大门
D. Tolmie, T. Boorman, A. DuBois, D. Dubois, Wu-chun Feng, I. Philp
{"title":"From HiPPI-800 to HiPPI-6400: A changing of the guard and gateway to the future","authors":"D. Tolmie, T. Boorman, A. DuBois, D. Dubois, Wu-chun Feng, I. Philp","doi":"10.1109/PI.1999.806412","DOIUrl":"https://doi.org/10.1109/PI.1999.806412","url":null,"abstract":"HiPPI-6400, a high-performance parallel interface running at 6400 Mb/s (800 MB/s), is a networking technology targeted for deployment in a local-area network (LAN) or system-area network (SAN). It is a low-latency, high-bandwidth switch that has the added features of providing flow control and error detection and retransmission in hardware, thus freeing network software from having to implement these functions. Due to the very low overhead of the HiPPI-6400 physical layer and the use of separate control lines, user data rates of HiPPI-6400 are literally 6400 Mb/s or 6.4 Gb/s (eight times the usable bandwidth of Gigabit Ethernet) with an achievable bit-error rate of less than 10/sup 25/. An initial 32-port HiPPI-6400 prototype, running an OS-bypass network protocol called ST between two 32-node SGI Origin 2000s, produced one-way latencies of 7 /spl mu/s and sustained data rates of 3.6 Gb/s (unidirectional) and 6.4 Gb/s (bidirectional). The HiPPI-6400 bandwidth in both cases was limited by the memory architecture of the SGI Origin 2000, not by the network. When running an OS-based protocol such as TCP, the unidirectional bandwidth was 2.2 Gb/s.","PeriodicalId":157032,"journal":{"name":"Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122035726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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