2009 IEEE International High Level Design Validation and Test Workshop最新文献_第2页

Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility 基于搜索状态兼容性的增量学习框架的硅诊断测试生成

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340172

M. Chandrasekar, M. Hsiao

{"title":"Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility","authors":"M. Chandrasekar, M. Hsiao","doi":"10.1109/HLDVT.2009.5340172","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340172","url":null,"abstract":"Silicon Diagnosis is the process of locating potential defect sites (candidates) in a defective chip. These candidates are then used as an aid during physical failure analysis. It is desired that the cardinality of the candidate set returned by silicon diagnosis be as small as possible. To this end, effective test patterns that can distinguish many faults in the candidate set is critical. Generation of such diagnostic patterns is referred to as Automatic Diagnostic Test Generation (ADTG). In this paper, we propose an aggressive and efficient learning framework for such a diagnostic test generation engine. It allows us to identify and prune non-trivial redundant search states thereby allowing to easily solve hard to distinguish or hard to prove equivalent fault pairs. Further, we propose an incremental flow for ADTG, where the information learned during detection-oriented test generation is passed to and incrementally used by ADTG. Experimental results on full-scan versions of ISCAS89/ITC99 circuits indicate that our method achieves up to 2x speed-up and/or resolves more initially unresolved fault pairs for most circuits.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131270963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Hardware Trojan: Threats and emerging solutions 硬件木马:威胁和新兴解决方案

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340158

R. Chakraborty, S. Narasimhan, S. Bhunia

引用次数: 390

Modular arithmetic decision procedure with auto-correction mechanism 具有自动纠错机制的模运算决策程序

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340162

B. Alizadeh, M. Fujita

引用次数: 1

STAR: Generating input vectors for design validation by static analysis of RTL STAR:通过RTL的静态分析生成设计验证的输入向量

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340179

Lingyi Liu, Shobha Vasudevan

引用次数: 31

PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis PowerRanger:使用基于sat的静态分析来评估电路对电源攻击的脆弱性

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340174

Jeff Hao, V. Bertacco

引用次数: 2

An instrumented observability coverage method for system validation 一种用于系统验证的可观测性覆盖方法

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340171

Peter Lisherness, K. Cheng

{"title":"An instrumented observability coverage method for system validation","authors":"Peter Lisherness, K. Cheng","doi":"10.1109/HLDVT.2009.5340171","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340171","url":null,"abstract":"In order to improve effectiveness and efficiency of post-silicon validation, we present a fault-symbol tracking method and a coverage metric that account for the limited observability in silicon and thus are useful for guiding validation test selection, test development, and design for debug. The coverage points targeted in this study are a set of fault-symbols, or ‘tags’, generated from each expression in a system model. Coverage is measured in simulation by tracking tags alongside dynamic information flows to user-defined or implicit observation points. Computation of the metric is performed based on high-level (C/C++) functional and behavioral models through compiler-inserted parallel fault-symbol tracking instrumentation, which offers high efficiency as well as compatibility with existing simulation flows. The coverage results from our initial implementation for a microcontroller instruction set simulator are compared with the statement and mutation coverages. The results show that the new coverage metric is more accurate than the statement coverage and can be computed in significantly shorter runtimes than the mutation coverage.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134567520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

MCBCG: Model Checking Based Sequential Clock-Gating MCBCG:基于模型检查的时序时钟门控

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340181

Sumit Ahuja, S. Shukla

{"title":"MCBCG: Model Checking Based Sequential Clock-Gating","authors":"Sumit Ahuja, S. Shukla","doi":"10.1109/HLDVT.2009.5340181","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340181","url":null,"abstract":"Dynamic power reduction techniques such as sequential clock-gating aim at eliminating inconsequential computation and clock-toggles of the registers. Usually sequential clock-gating opportunities are discovered manually based on certain characteristics of a design (e.g. pipelining). Since manual addition of sequential gating circuitry might change the functionality of the design, sequential equivalence checking is needed after such changes. Tools for sequential equivalence checking are expensive, and based on recent technologies. Therefore, it is desirable to automate the discovery of sequential clock-gating opportunities using already existing and proven technologies such as model checking and thereby a priori proving that the changes will not affect the required functionality. Model Checking Based Sequential Clock Gating (MCBCG) method formally proves particular sequential dependencies of registers on other registers and logic, thus sequentially gating such registers will not require further validation. An automation scheme for MCBCG methodology is also proposed in this paper. Preliminary experiments show up to 30% more savings than the traditional (combinational) clock-gating based power reduction techniques.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"54 96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124710939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Activity-based refinement for abstraction-guided simulation 针对抽象导向仿真的基于活动的细化

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340163

Debapriya Chatterjee, V. Bertacco

{"title":"Activity-based refinement for abstraction-guided simulation","authors":"Debapriya Chatterjee, V. Bertacco","doi":"10.1109/HLDVT.2009.5340163","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340163","url":null,"abstract":"Semi-formal verification tools are gaining popularity because of their ability to balance the performance of logic simulators with the goal-focused capabilities of formal verification. Within this domain, abstraction-based simulation is a technique that has been proposed in several research works and has also emerged in a few commercial solutions. Abstraction-based simulation performs reachability analysis on a design abstraction to gather approximate information on the distance of each design state from a goal state, and then uses this information in a guided search by the logic simulator. Unfortunately, so far, the quality of the abstraction has been the weakest link in this semi-formal solution, because of its impact in enabling a simulator to reach a verification goal. This paper presents a novel solution for abstraction refinement that operates in an abstraction-based simulation framework. Our solution collects switching activity information during simulation and determines how to modify and improve an abstraction based on analysis of this information. By using refinement, the original abstraction crafted by the tool is no longer a critical aspect of the semi-formal search. Instead, initially the abstraction may be weak, improving over time to enable the simulator to reach the goal state.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134594118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A symbolic execution framework for algorithm-level modelling 用于算法级建模的符号执行框架

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340168

Z. Hanna, T. Melham

{"title":"A symbolic execution framework for algorithm-level modelling","authors":"Z. Hanna, T. Melham","doi":"10.1109/HLDVT.2009.5340168","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340168","url":null,"abstract":"This work aims to address the well-known and acute challenge of functional validation for complex, contemporary microarchitectural circuit designs. We provide a new formal framework for algorithm level modelling—design modelling at a high abstraction level, focused exclusively on function and algorithms. The semantics of our models is based on Abstract State Machines with synchronous parallel execution, sequential execution, and nondeterminism. To express models we propose an executable, object-oriented Architecture Specification Language with rich data types and a well-defined formal semantics, based initially on Microsoft's AsmL. We describe an experimental framework for direct symbolic execution of models in this language, intended as a basis for both property and refinement verification, as well as design exploration. We explain and illustrate our approach through a case study, the modelling a simple μop scheduler and its refinement towards a design model for circuit implementation. We aim to show the utility of our language and symbolic execution framework for exploring microarchitectural algorithm and to validate designs using dynamic or formal techniques, yielding more productive convergence to high quality implementations.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129508274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality 利用等级性的分层编码在平行SMT决策过程中设计一种等价逻辑的独立策略

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340184

M. Velev, Ping Gao

{"title":"Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality","authors":"M. Velev, Ping Gao","doi":"10.1109/HLDVT.2009.5340184","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340184","url":null,"abstract":"With the number of processor cores in modern CPUs growing exponentially, it is expected that CPUs will have on the order of a hundred cores in the next 5 – 7 years. Thus, the need to implement parallel SMT decision procedures to utilize the increasing number of cores. We study a method to design independent strategies for a portfolio of parallel independent strategies in an SMT decision procedure for the logic of Equality with Uninterpreted Functions and Memories (EUFM). Particularly, our goal is to complement the previously used relative encoding (also called eij encoding) and logarithmic encoding of equations by exploiting hierarchical encodings of equations. Hierarchical encodings can have a wide variety of structures, where each level of the hierarchy uses a different simple encoding, and thus the potential for many possible translations to SAT with such encodings. Hierarchical encodings produced a speedup of at least an order of magnitude for an out-of-order superscalar processor with issue/retire width of 14 instructions per clock cycle, such that the speedup increases with the complexity of the microprocessor under formal verification.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122174558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7