PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis

Abstract

Cryptographic cores, though algorithmically secure, can leak information about their operation during execution. By monitoring the power dissipation of a core, an attacker can extract secret keys used for encryption. To guard against this, designers must minimize the variation of power dissipation of their circuits over time. Unfortunately, power dissipation is a complex function of several different factors, and an exhaustive search for its maximum range is computationally infeasible. In this paper, we propose PowerRanger, a technique based on Boolean satisfiability to produce tight upper and lower bounds on both maximum and minimum power dissipation. In addition, we incorporate min-cut partitioning in our solution to improve its scalability for large designs. We evaluated the quality and performance of PowerRanger on a number of ISCAS benchmarks, as well as two cryptographic cores, showing that our technique significantly outperforms previously known solutions.