2009 IEEE International High Level Design Validation and Test Workshop最新文献

A coordinated reachability analysis method for modular verification of asynchronous designs 异步设计模块化验证的协调可达性分析方法

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340165

Hao Zheng

引用次数: 0

Automated debugging with high level abstraction and refinement 具有高级抽象和细化的自动调试

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340178

Sean Safarpour, A. Veneris

引用次数: 0

Dynamic verification of Multicore Communication applications in MCAPI MCAPI中多核通信应用的动态验证

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340169

Subodh Sharma, G. Gopalakrishnan, Eric Mercer

引用次数: 3

A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces 高速串行接口验证、测试和调试的通用方案

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340167

Yongquan Fan, Z. Zilic

引用次数: 7

Design-for-debug for post-silicon validation: Can high-level descriptions help? 为调试而设计的后硅验证:高级描述有帮助吗?

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340159

N. Nicolici, Ho Fai Ko

引用次数: 14

TG-PRO: A new model for SAT-based ATPG TG-PRO:一种基于sat的ATPG新模型

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340173

Huan Chen, Joao Marques-Silva

{"title":"TG-PRO: A new model for SAT-based ATPG","authors":"Huan Chen, Joao Marques-Silva","doi":"10.1109/HLDVT.2009.5340173","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340173","url":null,"abstract":"Automatic Test Pattern Generation (ATPG) represents one of the first practical applications of Boolean Satisfiability (SAT). Even though ATPG can in general be considered easy for current state of the art SAT solvers, it is also the case that specific faults can be difficult to detect or prove undetectable, namely for large industrial circuits. Recent work on SAT-based ATPG has been motivated by industrial designs with ever increasing size, for which more efficient ATPG tools are essential. Moreover, ATPG models and algorithms find application in a number of other settings, that further motivate the development of more efficient SAT-based ATPG solutions. Interestingly, despite the potential interest of more efficient ATPG approaches, the core SAT-based ATPG model has remained essentially unchanged since it was first proposed in the late 80s. This paper proposes a new model for SAT-based ATPG. The proposed model is fundamentally different from previous SAT-based ATPG models in that the number of used variables is significantly reduced. Experimental results, obtained on a wide range of publicly available benchmarks, demonstrate that the new model allows significant performance improvements over other well-established models.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131502593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Fault table generation using Graphics Processing Units 使用图形处理单元生成故障表

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340175

Kanupriya Gulati, S. Khatri

{"title":"Fault table generation using Graphics Processing Units","authors":"Kanupriya Gulati, S. Khatri","doi":"10.1109/HLDVT.2009.5340175","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340175","url":null,"abstract":"In this paper, we explore the implementation of fault table generation on a Graphics Processing Unit (GPU). A fault table is essential for fault diagnosis and fault detection in VLSI testing and debug. Generating a fault table requires extensive fault simulation, with no fault dropping, and is extremely expensive from a computational standpoint. Fault simulation is inherently parallelizable, and the large number of threads that a GPU can operate on in parallel can be employed to accelerate fault simulation, and thereby accelerate fault table generation. Our approach, called GFTABLE, employs a pattern parallel approach which utilizes both bit-parallelism and thread-level parallelism. Our implementation is a significantly modified version of FSIM, which is pattern parallel fault simulation approach for single core processors. Like FSIM, GFTABLE utilizes critical path tracing and the dominator concept to reduce runtime. Further modifications to FSIM allow us to maximally harness the GPU's huge memory bandwidth and high computational power. Our approach does not store the circuit (or any part of the circuit) on the GPU. Efficient parallel reduction operations are implemented in our implementation of GFTABLE. We compare our performance to FSIM*, which is FSIM modified to generate a fault table on a single core processor. Our experiments indicate that GFTABLE, implemented on a single NVIDIA GeForce GTX 280 GPU card, can generate a fault table for 0.5 million test patterns on average 7.85x faster when compared with FSIM*. With the NVIDIA Tesla server, our approach would be potentially 34.82x faster.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114647983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

FLARE: A design environment for FLASH-based space applications FLARE:基于flash的空间应用的设计环境

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340180

M. Caramia, S. Carlo, M. Fabiano, P. Prinetto

引用次数: 6

IFRA: Post-silicon bug localization in processors IFRA:处理器中的后硅错误定位

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340160

Sung-Boem Park, S. Mitra

引用次数: 4

Localizing transient faults using dynamic bayesian networks 基于动态贝叶斯网络的暂态故障定位

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340170

Susmit Jha, Wenchao Li, S. Seshia

{"title":"Localizing transient faults using dynamic bayesian networks","authors":"Susmit Jha, Wenchao Li, S. Seshia","doi":"10.1109/HLDVT.2009.5340170","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340170","url":null,"abstract":"Transient faults are a major concern in today's deep sub-micron semiconductor technology. These faults are rare but they have been known to cause catastrophic system-level failures. Transient errors often occur due to physical effects on deployed systems and hence, diagnosis of transient errors must be performed over manufactured chips or systems assembled from black-box components where arbitrary instrumentation of the system is not possible and hence, the system state is only partially observable. Further, these systems are often composed of components that are third party IP which further adds opaqueness to the system. In this paper, we propose a probabilistic approach to localize transient faults in space and time for such partially observable systems. From a set of correct traces and a failure trace, we seek to locate the faulty component and the cycle of operation at which the fault occurred. Our technique uses correct system traces over monitored components of the system to learn a dynamic Bayesian network (DBN) summarizing the temporal dependencies across the monitored components. This DBN is augmented with different error hypotheses allowed by the fault model. The most probable explanation (MPE) among these hypotheses corresponds to the most likely location of the error. We evaluated the effectiveness of our technique on a set of ISCAS89 benchmarks and a router design used in on-chip networks in a multi-core design.","PeriodicalId":153879,"journal":{"name":"2009 IEEE International High Level Design Validation and Test Workshop","volume":"38 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131459969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15