IFRA: Post-silicon bug localization in processors

2009 IEEE International High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI:10.1109/HLDVT.2009.5340160

Sung-Boem Park, S. Mitra

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引用次数: 4

Abstract

IFRA overcomes challenges associated with an expensive step in post-silicon validation of processors - pinpointing the bug location and the instruction sequence that exposes the bug from a system failure. On-chip recorders collect instruction footprints (information about flows of instructions, and what the instructions did as they passed through various design blocks) during the normal operation of the processor in a post-silicon system validation setup. Upon system failure, the recorded information is scanned out and analyzed off-line for bug localization. Special self-consistency-based program analysis techniques, together with the test program binary of the application executed during post-silicon validation, are used. Major benefits of using IFRA over traditional techniques for post-silicon bug localization are: 1. It does not require full system-level reproduction of bugs, and, 2. It does not require full system-level simulation. Simulation results on a complex super-scalar processor demonstrate that IFRA is effective in accurately localizing electrical bugs with very little impact on overall chip area.

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IFRA:处理器中的后硅错误定位

IFRA克服了与处理器后硅验证的昂贵步骤相关的挑战-精确定位错误位置和从系统故障中暴露错误的指令序列。在后硅系统验证设置的处理器正常运行期间，片上记录器收集指令足迹(关于指令流的信息，以及指令在通过各种设计块时所做的事情)。当系统出现故障时，记录的信息将被扫描出来并离线分析以定位故障。使用了特殊的基于自一致性的程序分析技术，以及在硅后验证期间执行的应用程序的测试程序二进制文件。与传统技术相比，使用IFRA进行后硅bug定位的主要好处是:它不需要完整的系统级bug再现;它不需要完整的系统级仿真。在一个复杂的超标量处理器上的仿真结果表明，IFRA在对整个芯片面积影响很小的情况下，可以有效地精确定位电气缺陷。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2009 IEEE International High Level Design Validation and Test Workshop

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