Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility

Silicon Diagnosis is the process of locating potential defect sites (candidates) in a defective chip. These candidates are then used as an aid during physical failure analysis. It is desired that the cardinality of the candidate set returned by silicon diagnosis be as small as possible. To this end, effective test patterns that can distinguish many faults in the candidate set is critical. Generation of such diagnostic patterns is referred to as Automatic Diagnostic Test Generation (ADTG). In this paper, we propose an aggressive and efficient learning framework for such a diagnostic test generation engine. It allows us to identify and prune non-trivial redundant search states thereby allowing to easily solve hard to distinguish or hard to prove equivalent fault pairs. Further, we propose an incremental flow for ADTG, where the information learned during detection-oriented test generation is passed to and incrementally used by ADTG. Experimental results on full-scan versions of ISCAS89/ITC99 circuits indicate that our method achieves up to 2x speed-up and/or resolves more initially unresolved fault pairs for most circuits.