Proceedings of Fifth International Conference on Microelectronics for Neural Networks最新文献_第2页

Low power, low voltage conductance-mode CMOS analog neuron 低功耗，低电压电导模式CMOS模拟神经元

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493780

V. Fabbrizio, F. Raynal, X. Mariaud, A. Kramer, G. Colli

{"title":"Low power, low voltage conductance-mode CMOS analog neuron","authors":"V. Fabbrizio, F. Raynal, X. Mariaud, A. Kramer, G. Colli","doi":"10.1109/MNNFS.1996.493780","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493780","url":null,"abstract":"Analog implementations of neural networks have been used for a wide variety of tasks especially in the area of image processing. Typically, implementations of analog neural networks have been based on the use of either current or charge as the variable of computation. This work introduces a new class of analog neural network circuits based on the concept of conductance-mode computation. In this class of circuits, accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The advantages of this class of circuits are twofold: firstly, conductance-mode computation is fast-we have developed circuits based on these principles which compute at 5-10 MHz; secondly, because conductance-mode computation requires the minimum charge necessary to compare two conductances, its energy-consumption is self-scaling depending on the difficulty of the decision to be made-we have a working prototype which consumes 166 fJ per connection. The computing precision of these circuits is high: test results on a small test structure indicate an intrinsic precision of 8-9 bits. We have developed a larger test circuit which is able to perform computation with 1056 binary-valued inputs. Initial measurements in this large test structure indicate a more limited computing precision of 6+ to 8+ bits depending on the common mode of the input signal.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114867925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Pulsed VLSI for RBF neural networks RBF神经网络的脉冲VLSI

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493789

D. Mayes, A. Murray, H. Reekie

引用次数: 8

A SIMD/dataflow architecture for a neurocomputer for spike-processing neural networks (NESPINN) 面向峰值处理神经网络(NESPINN)的神经计算机SIMD/数据流架构

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493796

A. Jahnke, U. Roth, H. Klar

引用次数: 48

Teaching pulsed integrated neural systems: a psychobiological approach 教学脉冲综合神经系统:一种心理生物学方法

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493790

T. Lehmann

引用次数: 9

Motion detection silicon retina based on event correlations 基于事件相关性的运动检测硅视网膜

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493768

Pierre-François Ruedi

引用次数: 8

Topological mapping formation in a neural network with variations of device characteristics 具有器件特性变化的神经网络拓扑映射的形成

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493803

K. Tsuji, H. Yonezu, Jae-Kyun Shin

{"title":"Topological mapping formation in a neural network with variations of device characteristics","authors":"K. Tsuji, H. Yonezu, Jae-Kyun Shin","doi":"10.1109/MNNFS.1996.493803","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493803","url":null,"abstract":"The neural network of a human brain can well perform higher-order-information processing which could not be achieved by Neuman-type computers. In order to perform the processing, it is necessary to fabricate artificial neural systems which can form the topological mapping through learning. A new learning algorithm and a new network model have been proposed for fabrication by means of CMOS analog circuits with variations of device characteristics. The functions of those circuits were confirmed by means of SPICE simulations and the functions of PDM (pulse density modulator) were confirmed experimentally. The learning simulations of the network consisting of the circuits have also been carried out. The results show that the topological mapping is almost formed, even when variations of device characteristics exist in the neural network. The results also reveal that calculating the weighted sum of each neuron's potential and potentials of its surrounding neurons as the output of each neuron and adding proper number of redundant neurons to the output layer are effective mechanisms for the network with variations of device characteristics.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132354605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An analog floating-gate memory in a standard digital technology 一种标准数字技术中的模拟浮门存储器

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493802

T. Lande, H. Ranjbar, M. Ismail, Y. Berg

引用次数: 21

Spectral analysis and synthesis of three-layered feed-forward neural networks for function approximation 用于函数逼近的三层前馈神经网络的谱分析与合成

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493797

A. Pelagotti, V. Piuri

引用次数: 2

VIP: an FPGA-based processor for image processing and neural networks VIP:基于fpga的图像处理和神经网络处理器

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493811

Jocelyn Cloutier, Eric Cosatto, Steven Pigeon, R. Boyer, Patrice Y. Simard

引用次数: 55

Simulated annealing of binary fields using an optoelectronic circuit 利用光电电路模拟二元场的退火

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI: 10.1109/MNNFS.1996.493783

A. Dupret, J. Rodier, D. Prévost, E. Belhaire, P. Lalanne, P. Chavel, P. Garda

引用次数: 0