A SIMD/dataflow architecture for a neurocomputer for spike-processing neural networks (NESPINN)

Abstract

We present the architecture of a a neurocomputer for the simulation of spike-processing biological neural networks (NESPINN). It consists mainly of a neuron state memory, two connectivity units, a spike-event list, a sector unit and the NESPINN chip with a control unit, and eight PEs with 2 kB local on-chip memory each. In order to increase the performance features such as mixed SIMD/dataflow mode are included. The neurocomputer allows the simulation of up to 512 k neurons with a speed-up of ca. 600 over a Sparc-10. It thus allows tackling difficult low vision problems (e.g. scene segmentation) or simulation of the detailed spike behaviour of large cortical networks.