Proceedings of Fifth International Conference on Microelectronics for Neural Networks最新文献

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Application of terminal dynamics in cellular neural networks 终端动力学在细胞神经网络中的应用
C. Pacha, K. Goser
{"title":"Application of terminal dynamics in cellular neural networks","authors":"C. Pacha, K. Goser","doi":"10.1109/MNNFS.1996.493807","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493807","url":null,"abstract":"Terminal dynamics is a new nonlinear phenomenon based on the violation of the Lipschitz-condition. The characteristic features, like terminal attractors and repellers, are interesting for artificial neural networks. Because this subject was only discussed in a theoretical way, VLSI system concepts with terminal dynamics have not yet been developed. Therefore we combine the principles of terminal dynamics with cellular neural networks and illustrate our idea by means of a first application. An analog CMOS circuit operating in the subthreshold region is presented for a future VLSI implementation.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121923406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analog VLSI system for active drag reduction 模拟VLSI系统的主动减阻
B. Gupta, R. Goodman, F. Jiang, Y. Tai, S. Tung, Chih-Ming Ho
{"title":"Analog VLSI system for active drag reduction","authors":"B. Gupta, R. Goodman, F. Jiang, Y. Tai, S. Tung, Chih-Ming Ho","doi":"10.1109/MNNFS.1996.493771","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493771","url":null,"abstract":"We describe an analog CMOS VLSI system that can process real-time signals from surface-mounted shear stress sensors to detect regions of high shear stress along a surface in an airflow. The outputs of the CMOS circuit are used to actuate micromachined flaps with the goal of reducing this high shear stress on the surface and thereby lowering the total drag. We have designed, fabricated, and tested parts of this system in a wind tunnel in laminar and turbulent flow regimes.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"441 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122486465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
L-Neuro 2.3: a VLSI for image processing by neural networks L-Neuro 2.3:用于神经网络图像处理的VLSI
Marc Duranton
{"title":"L-Neuro 2.3: a VLSI for image processing by neural networks","authors":"Marc Duranton","doi":"10.1109/MNNFS.1996.493786","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493786","url":null,"abstract":"Real-time and embedded applications of image processing like pattern recognition, shape analysis etc. (using classical or less classical methods such as neural networks) are computer intensive tasks that lead to complex systems. Furthermore, the skyrocketting demand for those techniques has led to a flurry of algorithms that must be rapidly implemented, evaluated and finally tuned to real-world cases. This is why LEP has developed the fully programmable vectorial processor L-Neuro 2.3, which is a parallel chip composed of an array of twelve DSPs (Digital Signal Processors). It can be used for neurocomputing, fuzzy logics applications, real-time image processing, digital signal processing and all applications that can take advantage of cooperating DSPs. The now available chip is able to perform up to 2 Giga arithmetic operations per second, and has a peak throughput of 1.5 Gigabytes per second.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130802274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Array-based analog computation: principles, advantages and limitations 基于阵列的模拟计算:原理、优点和局限性
A. Kramer
{"title":"Array-based analog computation: principles, advantages and limitations","authors":"A. Kramer","doi":"10.1109/MNNFS.1996.493774","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493774","url":null,"abstract":"Analog implementations of neural networks and other computing architectures have gained increasing interest over the last decade. The field is at a critical juncture: continued interest will depend on the ability to demonstrate a clear advantage over digital solutions to problems of commercial interest. The neural network design group at SGS-Thomson Microelectronics has been working to explore the advantages and limitations of analog computation and implementations of neural network architectures. We are investigating 3 large-scale analog VLSI chips, all of which work on problems in image processing. The use of analog computing arrays, because of their efficiency and regularity, have formed the basis of most of our designs, while several different computing modes, including current, charge, and conductance have been explored. Another area in which we have focused is on the use of floating-gate flash-EEPROM devices for both non-volatile analog storage and computation. This paper will share insights into the lessons we have learned, the results we have achieved, and the limitations we have encountered. Particular emphasis will be made on two subjects: computational efficiency and equivalent precision of array-based analog computing circuits.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126560514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An analogue electronic model of Ventral Cochlear Nucleus neurons 耳蜗腹侧核神经元的模拟电子模型
A. V. Schaik, Eric Fragnière, Eric Vittoz
{"title":"An analogue electronic model of Ventral Cochlear Nucleus neurons","authors":"A. V. Schaik, Eric Fragnière, Eric Vittoz","doi":"10.1109/MNNFS.1996.493772","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493772","url":null,"abstract":"This paper proposes a simple analogue electronic spiking neuron circuit, which can be used to create hardware models of biological neural systems. In spite of its simplicity, the circuit is able to simulate a variety of different neuron types. Measurements of the neuron model in various settings am compared with the physiological response of certain neuron types in the Ventral Cochlear Nucleus, i.e., part of the first relay station in the brainstem of the auditory pathway. A good analogy between the response of the circuit and the different neurons has been obtained.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126372683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Retinomorphic vision systems 视胚视觉系统
K. Boahen
{"title":"Retinomorphic vision systems","authors":"K. Boahen","doi":"10.1109/MNNFS.1996.493766","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493766","url":null,"abstract":"The new generation of silicon retinae has two defining characteristics. First, these synthetic retinae are morphologically equivalent to their biological counterparts-at an appropriate level of abstraction. Second, they accomplish all four major operations performed by biological retinae using neurobiological principles: (1) continuous sensing for detection, (2) local automatic gain control for amplification, (3) spatiotemporal bandpass filtering for preprocessing, and (4) adaptive sampling for quantization. The author introduces the term retinomorphic to refer to this subclass of the neuromorphic electronic systems. Their design principles are compared and contrasted with the standard practice in imager design. It is argued that neurobiological principles are best suited to perceptive systems that go beyond reproducing the dynamic scene, like a conventional video camera does, to extracting salient information in real time. The results from a fully operational retinomorphic vision system are presented and the trade-offs involved in its design are discussed.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"602 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114259393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
A correlation-based network for hardware implementations 用于硬件实现的基于关联的网络
J. Ngole, L. Asplund
{"title":"A correlation-based network for hardware implementations","authors":"J. Ngole, L. Asplund","doi":"10.1109/MNNFS.1996.493799","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493799","url":null,"abstract":"An architecture and learning rules for a correlation-based network are proposed. Hidden activity predictors dynamically compute local temporal receptive field centres through a decorrelation process. Temporal feedback loops between units in the hidden layer are then used to synchronise the activities of similar near by units. The simultaneous activation of different topologically overlapping unit groupings results in a continual reorganisation of units in the hidden layer: the dependence of hidden intra-layer communication on cross-correlations gives it the image of an analogue spiking neural network. The predominantly feedforward nature of the architecture makes it attractive for implementation in parallel hardware. Some suggestions on how this can be accomplished are also proposed, together with some software simulation results on a problem of instantaneous separation of two sine waves with different phases.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116073232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A digital neural network LSI using sparse memory access architecture 采用稀疏存储器访问结构的数字神经网络LSI
K. Aihara, O. Fujita, K. Uchimura
{"title":"A digital neural network LSI using sparse memory access architecture","authors":"K. Aihara, O. Fujita, K. Uchimura","doi":"10.1109/MNNFS.1996.493784","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493784","url":null,"abstract":"A sparse memory access architecture is proposed to achieve a high-computational-speed neural network LSI. The architecture uses two key techniques, compressible synapse weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neurons. Calculations without an accuracy penalty. In a pattern recognition example, the number of memory accesses and neuron calculations are reduced to 0.87% of that in the conventional method and the practical performance is 18 GCPS.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114960380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Adaptive two-dimensional neuron grids 自适应二维神经元网格
A. Kronig, U. Ramacher
{"title":"Adaptive two-dimensional neuron grids","authors":"A. Kronig, U. Ramacher","doi":"10.1109/MNNFS.1996.493798","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493798","url":null,"abstract":"In the last decade many early-vision tasks have been cast into the form of global optimization principles: their solution is obtained by the minimization of appropriate cost functions. The minimization procedure, which consists in most cases of a simple gradient descent, often yields a two-dimensional particle model with local exchange interaction. Our starting point is a quite general representative of such a model, a two-dimensional neuron grid, which is based on a standard neuron model. The optimization principles enter our model via a backpropagation like adaption scheme for the weights. In the case of edge detection the results we arrive at so far are similar to those obtained by the gradient descent methods. So the formalism proposed here may form an alternative basis for more sophisticated image preprocessing algorithms.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115601765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The FAST architecture: a neural network with flexible adaptable-size topology FAST架构:一个具有灵活可适应大小拓扑结构的神经网络
A. Perez, E. Sánchez
{"title":"The FAST architecture: a neural network with flexible adaptable-size topology","authors":"A. Perez, E. Sánchez","doi":"10.1109/MNNFS.1996.493812","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493812","url":null,"abstract":"One of the central problems in the application of neural networks is finding the optimal network topology. This paper introduces the FAST architecture (flexible adaptable-size topology), an on-line, evolving neural network that dynamically adapts its topology through interactions with a problem-specific environment. We present a fully digital implementation of the network and demonstrate its viability on a pattern clustering task. We believe the FAST architecture holds potential by offering a fast, flexible platform for neural network applications.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123214722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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