A digital neural network LSI using sparse memory access architecture

Abstract

A sparse memory access architecture is proposed to achieve a high-computational-speed neural network LSI. The architecture uses two key techniques, compressible synapse weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neurons. Calculations without an accuracy penalty. In a pattern recognition example, the number of memory accesses and neuron calculations are reduced to 0.87% of that in the conventional method and the practical performance is 18 GCPS.