An analog floating-gate memory in a standard digital technology

T. Lande, H. Ranjbar, M. Ismail, Y. Berg
{"title":"An analog floating-gate memory in a standard digital technology","authors":"T. Lande, H. Ranjbar, M. Ismail, Y. Berg","doi":"10.1109/MNNFS.1996.493802","DOIUrl":null,"url":null,"abstract":"In this paper we present a simple CMOS analog memory structure using the floating gate of a MOS transistor. The structure is based on a special but simple layout which allows significant tunneling at relatively low voltage levels. The programming of the memory is achieved using the standard Fowler-Nordheim tunneling and is implemented in a standard digital CMOS process with only one polysilicon layer. A simple on-chip memory driver circuit is also presented. Experimental results from test chips fabricated in a standard 2-micron CMOS process show six orders of magnitude dynamic range in current for subthreshold operation.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNNFS.1996.493802","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21

Abstract

In this paper we present a simple CMOS analog memory structure using the floating gate of a MOS transistor. The structure is based on a special but simple layout which allows significant tunneling at relatively low voltage levels. The programming of the memory is achieved using the standard Fowler-Nordheim tunneling and is implemented in a standard digital CMOS process with only one polysilicon layer. A simple on-chip memory driver circuit is also presented. Experimental results from test chips fabricated in a standard 2-micron CMOS process show six orders of magnitude dynamic range in current for subthreshold operation.
一种标准数字技术中的模拟浮门存储器
本文提出了一种利用MOS晶体管浮栅的简单CMOS模拟存储器结构。该结构基于一种特殊但简单的布局,允许在相对较低的电压水平下进行显著的隧道掘进。存储器的编程是使用标准的Fowler-Nordheim隧道实现的,并在只有一个多晶硅层的标准数字CMOS工艺中实现。并给出了一种简单的片上存储器驱动电路。用标准的2微米CMOS工艺制作的测试芯片的实验结果显示,亚阈值操作的电流动态范围为6个数量级。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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