2010 15th CSI International Symposium on Computer Architecture and Digital Systems最新文献_第3页

Towards energy-scalable data centers 朝着能源可扩展的数据中心发展

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623534

B. Falsafi

引用次数: 0

Variation-aware task scheduling and power mode selection for MPSoC power optimization 变化感知任务调度和电源模式选择的MPSoC电源优化

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623596

M. Momtazpour, M. Goudarzi, Esmaeel Sanaei

引用次数: 1

M-ary parallel modular exponentiation: Software vs. hardware 并行模块化幂运算:软件vs.硬件

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623649

Sérgio de Souza Raposo, M. Santana, N. Nedjah, L. M. Mourelle

引用次数: 1

A modulo 2n+1 multiplier with double-LSB encoding of residues 残数双lsb编码的模2n+1乘法器

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623600

G. Jaberipur, H. Alavi

{"title":"A modulo 2n+1 multiplier with double-LSB encoding of residues","authors":"G. Jaberipur, H. Alavi","doi":"10.1109/CADS.2010.5623600","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623600","url":null,"abstract":"Modulo 2n+1 adders and/or multipliers are used in digital filters, cryptographic systems, and digital signal processors based on residue number systems (RNS). The moduli set {2n−1, 2n, 2n+1} is popular in RNS applications, where the design of modulo 2n+1 multipliers is more challenging than the case of other two moduli. One reason is that the natural representation of residues in the range [0, 2n] requires n+1 bits. However, a number of modulo 2n+1 addition or multiplication schemes have used n-bit diminished-1 representation of residues, where zero operands are supposed to be treated separately. On the other hand, double-LSB encoding of modulo 2n+1 residues (i.e., an n-bit code word with a second least significant bit) has been used in the design of an efficient modulo 2n+1 adder. We are therefore motivated to study the impact of the double-lsb encoding of residues on the design of modulo 2n+1 multipliers. We describe the operation of such multipliers in dot-notation representation and show that the corresponding circuitry uses only standard off the shelf arithmetic cells such as full adders, half adders and carry look-ahead logic. Synthesis based comparison with previously reported multipliers shows the advantages of the proposed design.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"8 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126272392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms 正位，负位，以及它们在有效实现算术算法中的混合使用

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623646

G. Jaberipur, B. Parhami

{"title":"Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms","authors":"G. Jaberipur, B. Parhami","doi":"10.1109/CADS.2010.5623646","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623646","url":null,"abstract":"Positively weighted and negatively weighted bits (posibits, negabits) have been used in the interpretation of 2's-complement, negative-radix, and binary signed-digit number representation schemes as a way of facilitating the development of efficient arithmetic algorithms for various application domains. In this paper, we show that a more general view of posibits and negabits, along with their mixed use in any combination (using inverse encoding for negabits), unifies a number of diverse implementation schemes, while at the same time making the resultant designs more efficient by avoiding custom or modified hardware elements and restricting the implementation to the use of standard arithmetic cells. Such standard cells have been highly optimized and are continually improving due to their wide applicability. Other practical benefits of our formulation include facilitation of low-voltage and low-power design, again due to the widespread availability of standard cells in variants optimized for low-voltage operation or energy economy. Pedagogical benefits include more intuitive explanations for a number of widely used transformations, such as Booth's recoding and column compression.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127350019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

High throughput low power CCMP architecture for very high speed wireless LANs 用于超高速无线局域网的高吞吐量低功耗CCMP架构

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623530

S. A. Hoseini, Behnam Khodabandeloo, Mahdi Jelodari Mamaghani, P. Teymoori, N. Yazdani

{"title":"High throughput low power CCMP architecture for very high speed wireless LANs","authors":"S. A. Hoseini, Behnam Khodabandeloo, Mahdi Jelodari Mamaghani, P. Teymoori, N. Yazdani","doi":"10.1109/CADS.2010.5623530","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623530","url":null,"abstract":"Considering the pervasion of wireless portable devices and growing trends in the use of multimedia applications, access to a high speed and, especially, a high throughput wireless channel are of significant importance. In addition to security concerns in wireless devices, deficiency in throughput and also increase in power consumption are introduced to the system by applying security. Therefore, designing a secure, high-speed wireless device with low power consumption would be a suitable response to worldwide demands. In this paper, we propose a solution to reduce encryption overhead and we almost eliminate it. Furthermore, a customized hardware architecture for Counter Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) is proposed. This protocol is the fundamental security architecture of IEEE 802.11i standard. To improve throughput and reduce overhead, encryption is accomplished in the spare time intervals, such as DCF Inter-Frame Spaces (DIFS) used in IEEE 802.11i standard. In order to overcome the restrictions in dealing with these time intervals, a multi-core structure is proposed. Moreover, to reduce power consumption, a particular scheduler is implemented for processing cores. In the proposed architecture, we achieve up to 2Gbps throughput in the single core mode for MPDU (MAC Protocol Data Unit) and A-MSDU (Aggregated MAC Service Data Unit) input frames, and 17Gbps throughput in multi core mode for A-MPDU (Aggregated MPDU) input frames.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121018392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Designing many-core platforms for silicon-efficient embedded multimedia computing 为高效硅嵌入式多媒体计算设计多核平台

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623542

L. Benini

引用次数: 0

Analysis of the soft error effects on CAN network controller 软误差对CAN网络控制器的影响分析

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623594

Saman Khoshbakht, H. Zarandi

引用次数: 0

Universal on-chip communication channel 通用片上通信通道

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623547

M. Rahimian, S. Mohammadi

引用次数: 2

A Quad Router design for next-generation CMPs 下一代cmp的四路路由器设计

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-09-01 DOI: 10.1109/CADS.2010.5623549

Hannaneh Aliee, H. Zarandi

引用次数: 0