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2010 15th CSI International Symposium on Computer Architecture and Digital Systems最新文献

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Proportionally fair buffer allocation in optical chip multiprocessors 光片多处理器中比例公平的缓冲区分配
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623523
Hessam Mirsadeghi, M. S. Talebi, A. Khonsari, M. Ould-Khaoua
{"title":"Proportionally fair buffer allocation in optical chip multiprocessors","authors":"Hessam Mirsadeghi, M. S. Talebi, A. Khonsari, M. Ould-Khaoua","doi":"10.1109/CADS.2010.5623523","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623523","url":null,"abstract":"Advances in CMOS-compatible photonic elements have made it plausible to exploit nanophotonic communication to overcome the limitations of traditional NoCs. In this paper, we consider buffer management as a resource allocation which can be cast as a convex optimization problem. Using this framework enables us to devise a token-based optimal buffer management algorithm in optical on-chip architecture that can address fairness issues, as well. The optimal buffer allocation algorithm can be implemented by a centralized controller that is supposed to send processor elements via a simple auxiliary embedded core. Simulation results confirm that the buffer allocation algorithm manages buffer space in a fair fashion as compared to simple naive schemes.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124428544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hardware-based Reliability Tree (HRT) for fault tree analysis 基于硬件的可靠性树(HRT)，用于故障树分析
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623587
Amir Rajabzadeh, M. S. Jahangiry
{"title":"Hardware-based Reliability Tree (HRT) for fault tree analysis","authors":"Amir Rajabzadeh, M. S. Jahangiry","doi":"10.1109/CADS.2010.5623587","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623587","url":null,"abstract":"Reliability analysis of critical systems is performed using fault trees. Fault trees are then converted to their equivalent Binary Decision Diagram, Cut Set, Markov Chain or Bayesian Network. These approaches however are complex and time consuming if a continuous time reliability curve is aimed, particularly for large systems. This paper introduces Hardware-based Reliability Tree (HRT). The HRT can be implemented by hardware in order to decrease reliability calculation time of a complex system. In this method, from a given fault tree, an equivalent Reliability Tree is generated and an equivalent hardware using op-amp, adder, gain, and multiplier circuits, is constructed. After obtaining continuous reliability curve over time, an integrator is utilized for calculating time to failure of the system. In order to evaluate the model, two systems were evaluated. The first one is a security alarm system and the second consists of two processors which share a single spare. In the case of failure of each processor, the spare is activated. Evaluation of these benchmarks using hardware implemented HRT demonstrates an speed up of up to 3.4E+6.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116965682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dynamic fault-tolerant wormhole routing in 2-D meshes 二维网格中的动态容错虫洞路由
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623538
A. Mortazavi, F. Safaei
{"title":"Dynamic fault-tolerant wormhole routing in 2-D meshes","authors":"A. Mortazavi, F. Safaei","doi":"10.1109/CADS.2010.5623538","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623538","url":null,"abstract":"With increasing probability of failure and reliability concerns for interconnection networks, fault-tolerance is quickly becoming an integral part of such systems. It is therefore critical to provide an efficient fault-tolerant mechanism to keep the system running, even in the presence of faults. In this paper a distributed fault-tolerant routing methodology for mesh networks is proposed which supports a dynamic fault model. Unlike most previous methods that support a dynamic fault model, the presented method is able to tolerate any number of faults with any shapes of fault regions without disabling healthy nodes. The performance of the method is extensively evaluated, and the results show that our proposed method is valid for mesh topology, which has graceful performance degradation and allows the network to remain fully operational facing with the failures.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116369439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reducing of soft error effects on a MIPS-based dual-core processor 减少基于mips的双核处理器的软错误影响
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623597
Moslem Didehban, Saman Khoshbakht, H. Zarandi, Saadat Pourmozaffari
{"title":"Reducing of soft error effects on a MIPS-based dual-core processor","authors":"Moslem Didehban, Saman Khoshbakht, H. Zarandi, Saadat Pourmozaffari","doi":"10.1109/CADS.2010.5623597","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623597","url":null,"abstract":"In this paper, a simulation-based fault injection analysis of a MIPS-based dual-core processor is presented, an approach is proposed to improve the reliability of most vulnerable parts of the processor components and then the improvement is evaluated. In the first series of experiments, a total of 9100 transient faults were injected in 114 different fault sites of the processor. These experiments demonstrate that the Message Passing Interface, the Arbiter and the Program Counters are the most vulnerable parts of the processor. Thus, these parts were selected as targets for the improvement. The fault tolerance method used for improving the Arbiter is based on using the Triple Modular Redundancy. As for the Message Passing Interface and the Program Counters the single bit error correction Hamming code is used. The experimental results show 11.8% improvement in error recovery and 15.1% reduction of failure rate at the cost of 1.01% area overhead.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132320804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Pipeline-based interlayer bus structure for 3D networks-on-chip 基于流水线的三维片上网络层间总线结构
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623524
M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen
{"title":"Pipeline-based interlayer bus structure for 3D networks-on-chip","authors":"M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1109/CADS.2010.5623524","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623524","url":null,"abstract":"The structure of direct vertical interconnections, called Through Silicon Vias (TSVs), is an important issue in the realm of 3D ICs. The bus-based and network-based structures are the two dominant architectures for implementing TSVs as interlayer connection in 3D ICs. Both implementations have some disadvantages. The former suffers from poor scalability and deteriorates the performance at high injection rates, and the latter consumes more area and power dissipation. In this paper, we propose a novel pipeline bus structure for TSVs to improve the performance of the prior bus-based architecture. The presented structure can utilize bi-synchronous FIFO for synchronization between stacked layers if each layer is fabricated by different technologies. Experimental results with synthetic test cases demonstrate that the proposed architecture gives significant improvements in average network latency. Also, the hardware area and power consumption of the presented bus structure are 9% and 11% less than the typical bus structure of TSVs, respectively.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126847714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Chip master planning: An efficient methodology to improve design closure and complexity management of ultra large chips 芯片总体规划:一种提高超大芯片设计封闭性和复杂性管理的有效方法
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623543
A. Jahanian, M. Saheb Zamani
{"title":"Chip master planning: An efficient methodology to improve design closure and complexity management of ultra large chips","authors":"A. Jahanian, M. Saheb Zamani","doi":"10.1109/CADS.2010.5623543","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623543","url":null,"abstract":"Mis-prediction is a dominant problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in failing the design cycle convergence. In this paper, a new planning methodology is presented in which a masterplan of the chip is constructed in early levels of physical design and the rest of succeeding physical design stags operate considering this masterplan. The proposed planning design flow is used to wire planning and buffer resource planning in order to compare with conventional contributions. Experimental results show the considerable improvements in terms of performance, timing yield and buffer usage.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122888635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sustainable digital infrastructure 可持续的数字基础设施
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623550
M. Pedram
{"title":"Sustainable digital infrastructure","authors":"M. Pedram","doi":"10.1109/CADS.2010.5623550","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623550","url":null,"abstract":"Modern society is built upon information and communications technologies that have permeated all aspects of our lives. Industries including e-commerce, healthcare, media, and finance are all dependent on network access to data and media services for their daily operations. Taken together, the hardware, software, and organizations that work together to provide network access, data storage, computation resources, and digital services constitute an information and communications infrastructure (ICI). As is the case with any true societal lifeline, ICI must be adaptable and available to changes and demands; and it must be energy-efficient and sustainable. It is this second requirement that will be the focus of my talk. In particular, I will begin by providing a broad definition of sustainability followed by a review of technology, system, and software solutions needed to achieve sustainable ICI.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131188913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An efficient power-area-delay modulo 2n−1 multiplier 一种高效的功率面积延迟模2n−1乘法器
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623593
S. Timarchi, M. Fazlali
{"title":"An efficient power-area-delay modulo 2n−1 multiplier","authors":"S. Timarchi, M. Fazlali","doi":"10.1109/CADS.2010.5623593","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623593","url":null,"abstract":"Carry propagation is a main problem in Residue Number System (RNS) arithmetic. This overhead can be eliminated by using redundant number representations which results in Redundant Residue Number System (RRNS). The RNS which uses Stored-Unibit-Transfer (SUT) encoding (SUT-RNS) has been shown as an efficient encoding for RRNS. In this paper, we first propose a general algorithm for radix-2h SUT-RNS digit multiplication. Then, we implement an efficient pipeline multiplier which is appropriate for frequent multiplications. The results indicate that the radix-8 SUT-RNS modulo 2n−1 multiplier outperforms area and power (energy/operation) of the previous efficient RRNS multipliers. Besides, it reaches the speed of the most high-speed RRNS multiplier.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123751942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Congestion-aware Network-on-Chip router architecture 感知拥塞的片上网络路由器架构
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623552
Chifeng Wang, Wen-Hsiang Hu, N. Bagherzadeh
{"title":"Congestion-aware Network-on-Chip router architecture","authors":"Chifeng Wang, Wen-Hsiang Hu, N. Bagherzadeh","doi":"10.1109/CADS.2010.5623552","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623552","url":null,"abstract":"This paper proposes a novel congestion-aware Network-on-Chip (NoC) architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also improves overall network throughput in various traffic scenarios. This congestion control scheme which consists of dynamic input arbitration and adaptive routing path selection is proposed to balance traffic load distribution so as to alleviate congestion caused by heavy network activities. Simulation results show that throughput is improved dramatically while maintaining superior latency performance for various traffic patterns. Cost evaluation results also show that congestion-aware router requires negligible cost overhead but provides better throughput for both mesh and diagonally-linked mesh NoC platforms.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"4 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Using Input-to-Output Masking for System-level Vulnerability estimation in high-performance processors 在高性能处理器中使用输入到输出掩蔽进行系统级漏洞估计
2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623540
Alireza Haghdoost, H. Asadi, A. Baniasadi
{"title":"Using Input-to-Output Masking for System-level Vulnerability estimation in high-performance processors","authors":"Alireza Haghdoost, H. Asadi, A. Baniasadi","doi":"10.1109/CADS.2010.5623540","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623540","url":null,"abstract":"In this paper, we enhance previously suggested vulnerability estimation techniques by presenting a detailed modeling technique based on Input-to-Output Masking (IOM). Moreover we use our model to compute the System-level Vulnerability Factor (SVF) for data-path components in a high-performance processor. As we show, recent suggested estimation techniques overlook the issue of error masking, mainly focusing on time periods in which an error could potentially propagate in the system. In this work we show that this is incomplete as it ignores the masking impact. Our results show that including the IOM factor can significantly affect the system-level vulnerability for data-path components. As a case study, we analyze the IOM factor for CPUs with different configurations. Our results show that the average variation of the IOM factor is less than 5%. Meantime, the IOM factor varies between 24% to 76% for the applications studied here. Accordingly we find the IOM factor to be less configuration dependent and mainly workload dependent.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125273876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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