An efficient power-area-delay modulo 2n−1 multiplier

S. Timarchi, M. Fazlali
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引用次数: 2

Abstract

Carry propagation is a main problem in Residue Number System (RNS) arithmetic. This overhead can be eliminated by using redundant number representations which results in Redundant Residue Number System (RRNS). The RNS which uses Stored-Unibit-Transfer (SUT) encoding (SUT-RNS) has been shown as an efficient encoding for RRNS. In this paper, we first propose a general algorithm for radix-2h SUT-RNS digit multiplication. Then, we implement an efficient pipeline multiplier which is appropriate for frequent multiplications. The results indicate that the radix-8 SUT-RNS modulo 2n−1 multiplier outperforms area and power (energy/operation) of the previous efficient RRNS multipliers. Besides, it reaches the speed of the most high-speed RRNS multiplier.
一种高效的功率面积延迟模2n−1乘法器
进位传播是剩余数系统(RNS)算法中的主要问题。这种开销可以通过使用冗余数字表示来消除,从而产生冗余剩余数系统(RRNS)。采用存储-单比特传输(SUT)编码(SUT-RNS)的RNS已被证明是一种有效的RRNS编码。本文首先提出了基数-2h SUT-RNS数字乘法的一般算法。然后,我们实现了一个适用于频繁乘法的高效管道乘法器。结果表明,基数为8的SUT-RNS模2n−1乘法器的面积和功率(能量/运算)都优于之前的高效RRNS乘法器。并且达到了目前最快的RRNS乘法器的速度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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