2010 15th CSI International Symposium on Computer Architecture and Digital Systems最新文献_第2页

A new compression ratio prediction algorithm for hardware implementations of LZW data compression 一种用于LZW数据压缩硬件实现的新的压缩比预测算法

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623592

Alireza Yazdanpanah, M. Hashemi

{"title":"A new compression ratio prediction algorithm for hardware implementations of LZW data compression","authors":"Alireza Yazdanpanah, M. Hashemi","doi":"10.1109/CADS.2010.5623592","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623592","url":null,"abstract":"As the demand for more data storage space continues to grow at an unprecedented pace, the need for real time data compression systems becomes more prominent. One of the well-known methods among lossless data compression algorithms is LZW. In this paper, a new prediction algorithm has been introduced that is able to predict whether or not a data block is compressible with the LZW method. Furthermore, the prediction algorithm provides a reasonably good estimation of the final compression ratio, hence helping the storage system decide early on whether or not to continue with the compression. Simulation results performed on several data compression corpuses indicate that the proposed prediction method is able to reduce run time by 17.79%, in average for a flash sector size of 8 KB. This is achieved at the expense of an average 1.59% decrease in compression performance. The difference between the predicted and actual compression ratio is 11.16% in average, in terms of mean absolute error. Considering the low computational complexity of the proposed method, it can be implemented with a relatively simple hardware hence making it suitable for real time, low-cost, and low-power hardware implementations.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134298078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Separating conflict misses to reduce miss-rate of caches through an unified replacement policy 通过统一的替换策略，分离冲突缺失，降低缓存缺失率

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623586

Hamed Azimi, A. Vafaei

引用次数: 0

Remaining-energy based routing protocol for wireless sensor network 基于剩余能量的无线传感器网络路由协议

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623532

Millad Ghane, Amir Rajabzadeh

引用次数: 5

Exploring a low-cost inter-layer communication scheme for 3D networks-on-chip 探讨三维片上网络的低成本层间通信方案

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623588

A. Rahmani, P. Liljeberg, J. Plosila, H. Tenhunen

引用次数: 3

CCDA: Correcting control-flow and data errors automatically CCDA:自动校正控制流和数据错误

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623537

M. Maghsoudloo, N. Khoshavi, H. Zarandi

{"title":"CCDA: Correcting control-flow and data errors automatically","authors":"M. Maghsoudloo, N. Khoshavi, H. Zarandi","doi":"10.1109/CADS.2010.5623537","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623537","url":null,"abstract":"This paper presents an efficient software technique to detect and correct control-flow errors through addition of redundant codes in a given program. The key innovation performed in the proposed technique is detection and correction of the control-flow errors using both control-flow graph and data-flow graph. Using this technique, most of control-flow errors in the program are detected first, and next corrected, automatically; so, both errors in the control-flow and program data which is caused by control-flow errors can be corrected. In order to evaluate the proposed technique, a post compiler is used, so that the technique can be applied to every 80×86 binaries, transparently. Three benchmarks quick sort, matrix multiplication and linked list are used, and a total of 5000 transient faults are injected on several executable points in each program. The experimental results demonstrate that at least 93% of the control-flow errors can be detected and corrected by the proposed technique automatically without any data error generation. Moreover, the performance and memory overheads of the technique are noticeably less than traditional techniques.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125595890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

OTRU: A non-associative and high speed public key cryptosystem OTRU:一种非关联的高速公钥密码系统

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623536

Ehsan Malekian, A. Zakerolhosseini

引用次数: 19

Performance evaluation of unicast and multicast communication in three-dimensional mesh architectures 三维网格结构中单播和组播通信的性能评价

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623591

M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen

引用次数: 3

Optimization and evaluation of the reconfigurable Grid Alu Processor 可重构网格Alu处理器的优化与评价

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623647

Basher Shehan, Ralf Jahr, S. Uhrig, T. Ungerer

{"title":"Optimization and evaluation of the reconfigurable Grid Alu Processor","authors":"Basher Shehan, Ralf Jahr, S. Uhrig, T. Ungerer","doi":"10.1109/CADS.2010.5623647","DOIUrl":"https://doi.org/10.1109/CADS.2010.5623647","url":null,"abstract":"Currently few architectural approaches propose new paths to raise the performance of conventional sequential instruction streams in the time of the billions transistor era. Many application programs could profit from processors that are able to speed up the execution of sequential applications beyond the performance of current superscalar processors. The Grid Alu Processor (GAP) is a runtime reconfigurable processor designed for the acceleration of a conventional sequential instruction stream without the need of recompilation. It comprises a superscalar processor front-end, a configuration unit, and an array of reconfigurable functional units (FUs), which is fully integrated into the pipeline. The configuration unit maps data dependent and independent instructions simultaneously at runtime into the array of FUs. This paper evaluates the GAP architecture and optimizes the hardware, the number of FUs, and the configuration layers implemented in the array. The simulations show a significant speed up for sequential applications on GAP in comparison to an out-of-order superscalar simulator (SimpleScalar). GAP outperforms SimpleScalar in average by about 50% on the basic architecture and about 100% with an extended version including configuration layers.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127025382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

On the design of new low-power CMOS standard ternary logic gates 新型低功耗CMOS标准三元逻辑门的设计

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623544

Akbar Doostaregan, M. H. Moaiyeri, K. Navi, O. Hashemipour

引用次数: 20

Dynamic voltage scaling for fully asynchronous NoCs using FIFO threshold levels 使用FIFO阈值水平的全异步noc动态电压缩放

2010 15th CSI International Symposium on Computer Architecture and Digital Systems Pub Date : 2010-11-09 DOI: 10.1109/CADS.2010.5623526

A. Rahimi, M. Salehi, S. Mohammadi, S. M. Fakhraie

引用次数: 4