可重构网格Alu处理器的优化与评价

Basher Shehan, Ralf Jahr, S. Uhrig, T. Ungerer
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引用次数: 2

摘要

目前,在数十亿晶体管时代,很少有架构方法提出新的途径来提高传统顺序指令流的性能。许多应用程序可以从能够加快顺序应用程序执行速度的处理器中获益,这种处理器的性能超过了当前的超标量处理器。栅格Alu处理器(GAP)是一种运行时可重构处理器,设计用于加速传统顺序指令流而无需重新编译。它包括一个超标量处理器前端、一个配置单元和一组可重构功能单元(FUs),这些可重构功能单元完全集成到管道中。配置单元在运行时将与数据相关的和独立的指令同时映射到fu数组中。本文对GAP体系结构进行了评估,并对该阵列的硬件、FUs数量和配置层进行了优化。仿真显示,与乱序超标量模拟器(SimpleScalar)相比,GAP上的顺序应用程序的速度有显著提高。GAP在基本架构上比SimpleScalar平均高出50%,在包含配置层的扩展版本上比SimpleScalar平均高出100%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimization and evaluation of the reconfigurable Grid Alu Processor
Currently few architectural approaches propose new paths to raise the performance of conventional sequential instruction streams in the time of the billions transistor era. Many application programs could profit from processors that are able to speed up the execution of sequential applications beyond the performance of current superscalar processors. The Grid Alu Processor (GAP) is a runtime reconfigurable processor designed for the acceleration of a conventional sequential instruction stream without the need of recompilation. It comprises a superscalar processor front-end, a configuration unit, and an array of reconfigurable functional units (FUs), which is fully integrated into the pipeline. The configuration unit maps data dependent and independent instructions simultaneously at runtime into the array of FUs. This paper evaluates the GAP architecture and optimizes the hardware, the number of FUs, and the configuration layers implemented in the array. The simulations show a significant speed up for sequential applications on GAP in comparison to an out-of-order superscalar simulator (SimpleScalar). GAP outperforms SimpleScalar in average by about 50% on the basic architecture and about 100% with an extended version including configuration layers.
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