A Quad Router design for next-generation CMPs

Abstract

This paper presents a router structure for Network-on-Chips called Quad Router which benefits from communication locality. The router can be shared among more than one Processing Element (PE), so the average hop count of a packet is decreased. This structure consists of eight input buffers and eight output ports by which two different topologies are introduced called Double-Link Mesh (DLM) and Crossbar Mesh (CM). In DLM topology, each Quad Router is connected to four immediate neighbors just like regular mesh topology, but with double links. In CM topology, each Quad Router is connected to eight neighbors in eight different directions. The main advantage of this architecture is reduction in packet latency because the PEs sharing a single Quad Router can connect directly to each other. Other advantages are drop in power and area overhead of the router. The experimental results show the effectiveness of the proposed topologies.