{"title":"残数双lsb编码的模2n+1乘法器","authors":"G. Jaberipur, H. Alavi","doi":"10.1109/CADS.2010.5623600","DOIUrl":null,"url":null,"abstract":"Modulo 2n+1 adders and/or multipliers are used in digital filters, cryptographic systems, and digital signal processors based on residue number systems (RNS). The moduli set {2n−1, 2n, 2n+1} is popular in RNS applications, where the design of modulo 2n+1 multipliers is more challenging than the case of other two moduli. One reason is that the natural representation of residues in the range [0, 2n] requires n+1 bits. However, a number of modulo 2n+1 addition or multiplication schemes have used n-bit diminished-1 representation of residues, where zero operands are supposed to be treated separately. On the other hand, double-LSB encoding of modulo 2n+1 residues (i.e., an n-bit code word with a second least significant bit) has been used in the design of an efficient modulo 2n+1 adder. We are therefore motivated to study the impact of the double-lsb encoding of residues on the design of modulo 2n+1 multipliers. We describe the operation of such multipliers in dot-notation representation and show that the corresponding circuitry uses only standard off the shelf arithmetic cells such as full adders, half adders and carry look-ahead logic. Synthesis based comparison with previously reported multipliers shows the advantages of the proposed design.","PeriodicalId":145317,"journal":{"name":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","volume":"8 Pt 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A modulo 2n+1 multiplier with double-LSB encoding of residues\",\"authors\":\"G. Jaberipur, H. Alavi\",\"doi\":\"10.1109/CADS.2010.5623600\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Modulo 2n+1 adders and/or multipliers are used in digital filters, cryptographic systems, and digital signal processors based on residue number systems (RNS). The moduli set {2n−1, 2n, 2n+1} is popular in RNS applications, where the design of modulo 2n+1 multipliers is more challenging than the case of other two moduli. One reason is that the natural representation of residues in the range [0, 2n] requires n+1 bits. However, a number of modulo 2n+1 addition or multiplication schemes have used n-bit diminished-1 representation of residues, where zero operands are supposed to be treated separately. On the other hand, double-LSB encoding of modulo 2n+1 residues (i.e., an n-bit code word with a second least significant bit) has been used in the design of an efficient modulo 2n+1 adder. We are therefore motivated to study the impact of the double-lsb encoding of residues on the design of modulo 2n+1 multipliers. We describe the operation of such multipliers in dot-notation representation and show that the corresponding circuitry uses only standard off the shelf arithmetic cells such as full adders, half adders and carry look-ahead logic. Synthesis based comparison with previously reported multipliers shows the advantages of the proposed design.\",\"PeriodicalId\":145317,\"journal\":{\"name\":\"2010 15th CSI International Symposium on Computer Architecture and Digital Systems\",\"volume\":\"8 Pt 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 15th CSI International Symposium on Computer Architecture and Digital Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CADS.2010.5623600\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 15th CSI International Symposium on Computer Architecture and Digital Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CADS.2010.5623600","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A modulo 2n+1 multiplier with double-LSB encoding of residues
Modulo 2n+1 adders and/or multipliers are used in digital filters, cryptographic systems, and digital signal processors based on residue number systems (RNS). The moduli set {2n−1, 2n, 2n+1} is popular in RNS applications, where the design of modulo 2n+1 multipliers is more challenging than the case of other two moduli. One reason is that the natural representation of residues in the range [0, 2n] requires n+1 bits. However, a number of modulo 2n+1 addition or multiplication schemes have used n-bit diminished-1 representation of residues, where zero operands are supposed to be treated separately. On the other hand, double-LSB encoding of modulo 2n+1 residues (i.e., an n-bit code word with a second least significant bit) has been used in the design of an efficient modulo 2n+1 adder. We are therefore motivated to study the impact of the double-lsb encoding of residues on the design of modulo 2n+1 multipliers. We describe the operation of such multipliers in dot-notation representation and show that the corresponding circuitry uses only standard off the shelf arithmetic cells such as full adders, half adders and carry look-ahead logic. Synthesis based comparison with previously reported multipliers shows the advantages of the proposed design.