International Symposium on Microelectronics最新文献

{"title":"Photonic Debonding for Wafer-Level Packaging","authors":"V. Turkani, V. Akhavan, K. Schroder, Xiao Liu, Luke Prenger, Xavier Martinez","doi":"10.4071/1085-8024-2021.1.000067","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000067","url":null,"abstract":"\u0000 Temporary bonding and debonding (TB/DB) processes have emerged as promising solutions in wafer-level packaging technology. These processes offer a pathway to wafer thinning and subsequent backside processing, which are crucial in enabling heterogenous integration using technologies such as 3D through-silicon-vias (TSVs) and fan-out wafer-level packaging. These are critical for overall device miniaturization and increased performance. In this work, a novel photonic debonding (PDB) method and the corresponding bonding material are presented. PDB enhances the TB/DB process by overcoming many of the disadvantages associated with traditional debonding methods. PDB uses pulsed broadband light (200 nm – 1100 nm) from flashlamps to debond temporarily bonded wafer pairs with glass as the carrier wafer. These flashlamps generate high-intensity pulses of light (up to 45 kW/cm2) over short time intervals (~100 μs) to facilitate the debonding. Feasibility of the PDB in the TB/DB process is demonstrated by successfully debonding thinned (<70 μm) silicon wafers from glass carriers. Post-debond cleaning of the thinned wafers and carriers is evaluated. With uniform, large-area illumination (75 mm x 150 mm) per flashlamp and with the ability to concatenate lamps to increase the illumination area of the PDB tool, the PDB method offers a high-throughput and low-cost debonding solution for both wafer-level and panel-level packaging technologies.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89636968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Transmission Loss Cu Wirings with Smooth Seed Layer and High Adhesion against Prepregs","authors":"Kazue Hirano, Masaya Toba, Masaki Yamaguchi","doi":"10.4071/1085-8024-2021.1.000308","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000308","url":null,"abstract":"\u0000 Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by semi-additive process (SAP) with desmear process and/or modified semi-additive process (MSAP) by using Cu foil with large surface roughness. Though a desmear process and Cu foil can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of that processes, we applied an UV modification for the surface of our developed prepreg in order to realize a smooth and high adhesive seed layer against the dielectric. We also conducted chemical modification for the surface of Cu foil to achieve low attenuation of transmission loss and high adhesion against prepreg. We successfully assembled Cu wirings with L/S = 6/6 μm on prepregs by SAP. High peel strength between Cu foil and prepreg was obtained due to chemical modification for the surface of Cu foil. The normalized transmission loss of Cu wiring assembled through MSAP was improved as compared to Cu foil with rough surface.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78808689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Implementation of Harmonic RFID Based on Conventional UHF System","authors":"Aditya Purandare, Yihang Chu, Deepak Kumar, Saikat Mondal, A. Mason, P. Chahal","doi":"10.4071/1085-8024-2021.1.000176","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000176","url":null,"abstract":"\u0000 There has been growing interest in the use of passive harmonic RFIDs for diverse range of applications. Conventional RFIDs are prone to self-jamming and multipath interference, and these challenges can be mitigated using the harmonic RFID design. Recently several harmonic RFID designs have been demonstrated. However, there are many designs related, packaging and intellectual property challenges associated with new tag designs. It has been well known that conventional RFIDs produce harmonic content, which is typically suppressed to reduce background noise. Previous experiments have demonstrated that the harmonics generated by conventional RFIDs can be utilized to enhance their performance. In this paper, an RFID chip is characterized for the generation of harmonic frequencies. This is carried out by designing a high frequency board that contains calibration structures along with structures to characterize the RFID chip using a one port network. An equivalent model is then developed, which in turn is used to design a dual band antenna that works at the fundamental and harmonic frequencies. In addition, the conventional RFID interrogator is modified to accommodate the measurement of harmonics generated by the RFIDs. A complete harmonic tag system is designed and implemented, and an example application of harmonic RFID is demonstrated. Here, the harmonic RFID tag is used in an industrial setting where there is large clutter (large reflections from metal structures).","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"16 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79300584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Alternative FCBGA Package Solution Evaluation: High-speed Design Optimization and Electrical Characterization of FOBGA","authors":"Hung-Hsiang Cheng, Cheng-Yu Wu, H. Kuo, Chen-Chao Wang, Guo-Cheng Liao, Yun-Hsiang Tien, Yi-Chuan Ding","doi":"10.4071/1085-8024-2021.1.000119","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000119","url":null,"abstract":"\u0000 There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV SoCs. The other package solution is Fan-out Ball Grid Array (FOBGA) which is targeting larger FCBGA with high ABF layer count. The focused maximum package size and layer count of FCBGA are 55 mm x 55 mm and 6+2+6L individually. The potential applications are CPUs, AI accelerators, and networking switches which require extremely high electrical performance. The design concept of FOBGA is to redistribute signal bump locations on FO die, and make an ABF substrate layer accommodate more I/O signals to further reduce the layer count of the ABF substrate. The package signal integrity (SI) and power integrity (PI) analyses are performed to validate the electrical performance of proposed package solutions. Finally, we come out with design guidelines of FOBGA to mitigate the performance degradation due to substrate layer reduction.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"143 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87966718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Constraints and Scale Down Evolution in Advanced Semiconductor Packages","authors":"B. Kim, Sanghyeon Lee, JaeBeom Shim, N. Cho, JinYoung Khim","doi":"10.4071/1085-8024-2021.1.000006","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000006","url":null,"abstract":"\u0000 Wafer fabrication (fab) technology has been scaling down for several decades but now faces many barriers to overcome in terms of technology as well as economy. Beyond Moore's law, the scaling becomes a question of how to cost effectively integrate more functions and achieve better performance. For this matter, the semiconductor industry is looking for packaging solutions using system-on-chip (SoC) or System in Package (SiP) technologies.\u0000 In this paper, using a commercial mobile application processor (AP), design factors for package integration have been identified and the next level of integration will be proposed by design simulation. The commercial mobile AP package is a good candidate for identifying major design factors because it has evolved in both fab processing and package-level design over many years. Package platform has evolved from a single package to a stack die package and Package-on-Package (PoP) structure. As it is scaled down and interfaced more closely with memory, package technology has evolved but now faces various challenges in structure along with many design constraints. To address these issues, the major drivers and design challenges in package technology will be identified and future direction be proposed.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"91 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89389691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Emergence of Glass Solutions for 5G and Heterogeneous Integration","authors":"A. Shorey, S. Nelson, D. Levy, P. Ballentine","doi":"10.4071/1085-8024-2021.1.000298","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000298","url":null,"abstract":"\u0000 Glass has been of great interest for advanced packaging and RF applications for many years. Since glass is an insulator, it provides low loss performance particularly at high frequencies in the mmWave. The low roughness and ability to form in thin and large area formats provide opportunities for fine line spacing to enable miniaturization and cost-effectiveness. The challenge to glass adoption has been to establish high volume manufacturing operations. Leveraging the Viaffirm® temporary bond process provides many advantages to enable use of existing processes to fabricate thin glass substrates. Here we describe the process and examples of how it has been used to enable manufacture of devices on thin glass substrates.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"51 1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78418088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"JEDEC's Generation of Wire Bond Pull Test Methods to Address Pulling of Copper Wire Bonds","authors":"Curtis Grosskopf","doi":"10.4071/1085-8024-2021.1.000249","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000249","url":null,"abstract":"\u0000 More than 50 years ago when the wire pull test method was initially added to Mil-Std 883, in Condition D of Method 2011, Bond Strength (Destructive Bond Pull Test), the test procedure and minimum pull force values were based on pull testing of mostly ultrasonic wedge bonded aluminum and gold wires of just a few different diameters. The minimum pull force values from that original data were extrapolated to cover a much wider range of wire diameters for both gold and aluminum wires. Since the release of this test method the electronics industry has manufactured copper ultrasonic wedge bonds, widely adopted copper thermosonic ball bonding roughly 15 years ago, and even developed a niche market for silver thermosonic ball bonding. The industry also developed specialty bonds such as security bonds, reverse bonds also called \"stitch on ball\", and even multi-loop wires and ribbons. In all that time neither the test procedure nor the minimum pull force values in Method 2011 were reviewed to determine their appropriateness for these new materials or new types of bonds, even though the industry widely referenced the test method for all of them and thus, by default, accepted its use for all of them.\u0000 In late 2013, I led a working group within JEDEC's JC14.1 subcommittee, Reliability Test Methods for Packaged Devices, to update JEDEC JESD22-B116, Ball Bond Shear Test Method, to expand its scope to include the shearing of Cu ball bonds. It took the working group three years to address the necessary technical issues to ensure that the revised test method adequately addressed the shearing of copper ball bonds and propose minimum acceptable shear values. The working group produced a greatly improved document with drawings and images depicting the different shear fail modes of both gold and copper bonds and added several informative annexes to aid in the performing of the test method.\u0000 By 2018 it was apparent that none of the most commonly referenced wire pull test methods in the electronics industry had made any significant progress in updating their documents to include Cu wire bonds. Therefore, the JC14.1 working group agreed to work jointly with the JC-13.7 Subcommittee, New Electronic Device Technology, to create a new, wire pull test method document under JC14.1 that would be a companion to the JESD22-B116. This new document will use Method 2011, Conditions C and D as its basis, but expand on its scope to cover copper wire bonds, both ultrasonic wedge and thermosonic ball bonds. The new test method will describe the process for a ball pull test and a stitch pull test that are referenced for copper bonds by AEC Q006, Qualification Requirement for Component Using Copper (Cu) Wire Interconnection. The test method will also provide guidance on how to perform pull testing on several different bond types used today including reverse bonds, multi-loop bonds, and stacked die. The working group plans to propose minimum pull values for copper wire bonds which JC14.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"8 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76979890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Additively Manufactured Extreme Temperature Electronics Packaging","authors":"D. Shaddock, C. Hoel, N. Stoffel, M. Poliks, M. Alhendi","doi":"10.4071/1085-8024-2021.1.000189","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000189","url":null,"abstract":"\u0000 There is growing interest in extreme temperature electronics to support the mission needs to sense, actuate, and communicate at temperatures beyond the normal range of operations in commercial and military applications. Reliable packaging in the temperature range of more than 300°C has been demonstrated using ceramic multi-chip modules using conventional hybrid circuit technology. This approach typically requires high NRE costs and lead time. Additive manufacturing processes of metals, ceramics, conductors, and dielectrics provides a digital transformation of hybrid circuit manufacturing technology that reduces time and cost for packaging with the added benefits of novel 3D structures and embedded features. This report presents the results of testing to characterize important electrical and mechanical properties of additively manufactured packaging materials (substrates, conductor, dielectrics) and die interconnect methods needed for 300 to 750 °C electronic packaging designs.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74907657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Copper Crystal Structures in Plated Microvias. Their Recrystallisation and a Means to Identify Joints at Risk of Premature Failure","authors":"T. Bernhard, R. Massey, K. Klaeden, S. Zarwell, S. Kempa, E. Steinhaeuser, S. Dieter, F. Brüning","doi":"10.4071/1085-8024-2021.1.000292","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000292","url":null,"abstract":"\u0000 Plated microvias are widely used within todays PCB industry as a means of achieving the high-density designs that are required in modern mobile devices, however, there has been growing concern regarding their long term reliability performance when stacked directly on top of each other.\u0000 Blind microvias (BMV) have a potentially complex metallurgical structure, with several interfaces located around the target pad - electroless Copper - electrolytic Copper joint. While field experience as shown that there are typically two major types of crystal structures formed across the BMV base, there has been little reported work investigating how or why such structures develop. In this paper, we review these two commonly observed microstructures within filled BMVs and offer proposals on how such structures are created. We subsequently describe a novel means to indicate if the microstructure of a BMV is likely to have a tendency for an early onset of failure.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"107 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74918148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Novel SAC-Bi Solder Joints on Electromigration Reliability for Wafer Level Chip Scale Packages","authors":"M. Tsai, Yung-Sheng Lin, C. Kao, Shan-Bo Wang, T. Lin, Y. Hung","doi":"10.4071/1085-8024-2021.1.000136","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000136","url":null,"abstract":"\u0000 The Sn-4Ag-0.5Cu base solder adding 3 wt.% bismuth (SAC-3Bi) solder has better drop and thermal cycling performance than Sn-4Ag-0.5Cu solder due the excellent mechanical properties in previous study. Therefore, SAC-3Bi has applied in solder joints of wafer level chip scale packaging (WLCSP) in recent year. In this study, SAC-3Bi solder was used on WLCSP device to evaluate electromigration reliability. A specially designed test vehicle for SAC-3Bi solder balls with 200μm diameter Ti/Cu/Cu UBM have been investigated experimentally. The electromigration behavior of solder balls was investigated in terms of the electrical resistance change, and the mechanism was also explored by the microstructure evolutions. The electromigration experiment of the SAC-3Bi solder balls was conducted continuously at 1.2 A to 1.6 A under 170 °C to 185 °C condition. The resistance of solder balls was monitored according to Kelvin structure. An EM prediction model of SAC-3Bi solder balls was built based on Black-type electromigration time to failure equation, followed the JEDEC with five test conditions. The activation energy of SAC-3Bi solder is 0.80 eV ± 0.02 eV, coinciding the activation energy of SAC based solder alloy (0.72 eV ~ 0.89 eV). The microstructure of the solder balls was investigated using a scanning electron microscope (SEM) accompanying energy-dispersive X-ray spectroscopy (EDS) and electron backscatter diffraction (EBSD) for the failure behaviors and phase characterization. There were intermetallic compounds of Cu3Sn and Cu6Sn5 at the interface of copper and solder. We observed two failure modes of SAC-3Bi solder balls during current stressing, the fracture occurred at the UBM/solder ball interface and Cu redistribution layer (RDL), respectively. The failure mechanisms have been investigated in detail from microstructure analysis.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"109 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76095165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}