Design Constraints and Scale Down Evolution in Advanced Semiconductor Packages

Abstract

Wafer fabrication (fab) technology has been scaling down for several decades but now faces many barriers to overcome in terms of technology as well as economy. Beyond Moore's law, the scaling becomes a question of how to cost effectively integrate more functions and achieve better performance. For this matter, the semiconductor industry is looking for packaging solutions using system-on-chip (SoC) or System in Package (SiP) technologies. In this paper, using a commercial mobile application processor (AP), design factors for package integration have been identified and the next level of integration will be proposed by design simulation. The commercial mobile AP package is a good candidate for identifying major design factors because it has evolved in both fab processing and package-level design over many years. Package platform has evolved from a single package to a stack die package and Package-on-Package (PoP) structure. As it is scaled down and interfaced more closely with memory, package technology has evolved but now faces various challenges in structure along with many design constraints. To address these issues, the major drivers and design challenges in package technology will be identified and future direction be proposed.