Proceedings of the 2016 International Symposium on Low Power Electronics and Design最新文献_第4页

Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization 通过变化感知微处理器管道优化最大化NTC的能源效率

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934635

A. Gebregiorgis, M. Golanbari, S. Kiamehr, Fabian Oboril, M. Tahoori

{"title":"Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization","authors":"A. Gebregiorgis, M. Golanbari, S. Kiamehr, Fabian Oboril, M. Tahoori","doi":"10.1145/2934583.2934635","DOIUrl":"https://doi.org/10.1145/2934583.2934635","url":null,"abstract":"Near threshold computing (NTC) has the potential to reduce the energy consumption by orders of magnitude. However, NTC designs suffer from a higher sensitivity to process variation and substantial performance degradation. In NTC, process variation affects the delays of different pipeline stages significantly, resulting in energy-inefficient designs. In this paper, we propose an energy-efficient variation-aware processor pipeline optimization, in which the pipeline stages are balanced by considering the impact of process variation during earlier design phases. This can lead to a well-balanced design and significant improvement in energy-efficiency. For this purpose, we employ an iterative variation-aware synthesis flow in which the synthesis tool is provided with variation information. Since the impact of process variation is considered during synthesis, our technique can improve the energy-efficiency by avoiding pessimistic guard band. Simulation results show that our technique can improve the energy-efficiency of OpenSPARC and FabScalar cores by 55% and 85%, respectively.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128281685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Session details: Dynamic Power and Thermal Management 会议细节:动态电源和热管理

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/3256022

Parth Malani, A. Raghunathan

引用次数: 0

A Li-Ion Battery Charge Protocol with Optimal Aging-Quality of Service Trade-off 一种最优老化-服务质量权衡的锂离子电池充电协议

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934591

Yukai Chen, Alberto Bocca, A. Macii, E. Macii, M. Poncino

{"title":"A Li-Ion Battery Charge Protocol with Optimal Aging-Quality of Service Trade-off","authors":"Yukai Chen, Alberto Bocca, A. Macii, E. Macii, M. Poncino","doi":"10.1145/2934583.2934591","DOIUrl":"https://doi.org/10.1145/2934583.2934591","url":null,"abstract":"The reduction of usable capacity of rechargeable batteries can be mitigated during the charge process by acting on some stress factors, namely, the average state-of-charge (SOC) and the charge current. Larger values of these quantities cause an increased degradation of battery capacity, so it would be desirable to keep both as low as possible, which is obviously in contrast with the objective of a fast charge. However, by exploiting the fact that in most battery-powered systems the time during which it is plugged for charging largely exceeds the time required to charge, it is possible to devise appropriate charge protocols that achieve a good balance between fast charge and aging. In this paper we propose a charge protocol that, using an accurate estimate of the charging time of a battery and the statistical properties of the charge/discharge patterns, yields an optimal trade-off between aging and quality of service. The latter is measured in terms of the distance of the actual SOC from 100% at the end of the charge phase. Results show that the present method improves significantly over other similar protocols proposed in the literature.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125858577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Terahertz Technology and its Applications: Is it All Hype? 太赫兹技术及其应用:都是炒作吗?

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2962722

G. Chattopadhyay

{"title":"Terahertz Technology and its Applications: Is it All Hype?","authors":"G. Chattopadhyay","doi":"10.1145/2934583.2962722","DOIUrl":"https://doi.org/10.1145/2934583.2962722","url":null,"abstract":"For more than last forty years, terahertz components and instruments have primarily been developed for space science applications in radio astronomy and planetary sciences. However, in recent years, terahertz waves are increasingly being used in commercial applications such as high speed communications, security imaging, autonomous landing and refueling of airplanes, and medicines. In spite of all these fascinating scientific and commercial potential, the terahertz frequency range (loosely defined as 300 GHz < v < 10 THz) still remains one of the least utilized electromagnetic bands because of the unavailability of commercial source and sensor components, and sub-systems. Recent progress in CMOS technology as well as availability of InP HEMT based amplifiers in terahertz frequency band has caught the imagination of researchers for developing terahertz instruments for commercial applications. Rapid progress in multiple fronts, such as commercial software for component and device modeling, low-loss waveguide circuits and interconnect technologies, silicon micromachining for highly integrated and compact packaging, and submicron scale lithographic techniques, is making it an exciting time for terahertz engineers and scientists. In this presentation, an overview of the state of the terahertz technology will be presented. The talk will detail the science and other applications that specifically require low-power technology at terahertz frequencies. The challenges of the future generation instruments and detectors at these frequencies in addressing the needs for critical scientific and commercial applications will also be discussed. The research described herein was carried out at the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California, USA, under contract with National Aeronautics and Space Administration.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125085340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches 利用互补电阻性开关的电阻性存储器的原位修复

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934590

A. Ghofrani, M. Lastras-Montaño, Yuyang Wang, K. Cheng

{"title":"In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches","authors":"A. Ghofrani, M. Lastras-Montaño, Yuyang Wang, K. Cheng","doi":"10.1145/2934583.2934590","DOIUrl":"https://doi.org/10.1145/2934583.2934590","url":null,"abstract":"Recent advances in resistive memory technologies have demonstrated their potential to serve as next generation random access memories (RAM) which are fast, low-power, ultra-dense, and nonvolatile. However, owing to their stochastic filamentary nature, several sources of hard errors exist that could affect the lifetime of a resistive RAM (ReRAM). In this paper, we propose a novel mechanism to protect resistive memories against hard errors through the exploitation of a unique feature of bipolar resistive memory elements. Our solution proposes an unorthodox use of complementary resistive switches (a particular implementation of resistive memory elements) to provide an \"in-place spare\" for each memory cell at negligible extra cost. The in-place spares are then utilized by our repair scheme to extend the lifetime of a resistive memory. Our repair scheme detects data errors during regular memory accesses and triggers repair using the in-place spares at a page-level granularity. We show that in-place spares can be used along with other memory reliability and yield enhancement solutions, such as error correction codes (ECC) and spare rows. We develop a statistical model to evaluate our method's effectiveness on extending ReRAM's lifetime. Our analysis shows that the in-place spare scheme can roughly double the lifetime of a ReRAM system. Alternatively, our method can yield the same lifetime as a baseline ReRAM, with either significantly fewer spare rows or a lighter-weight ECC, both of which can save on energy consumption and area.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124196591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection 库存:用于低开销近似错误检测的随机检查器

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934634

Neel Gala, Swagath Venkataramani, A. Raghunathan, V. Kamakoti

{"title":"STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection","authors":"Neel Gala, Swagath Venkataramani, A. Raghunathan, V. Kamakoti","doi":"10.1145/2934583.2934634","DOIUrl":"https://doi.org/10.1145/2934583.2934634","url":null,"abstract":"Designing reliable systems, while eschewing the high overheads of conventional fault tolerance techniques, is a critical challenge in the deeply scaled CMOS and post-CMOS era. To address this challenge, we leverage the intrinsic resilience of application domains such as multimedia, recognition, mining, search, and analytics where acceptable outputs are produced despite occasional approximate computations. We propose stochastic checkers, wherein a stochastic logic based realization of the circuit is used as an error checker, and the original circuit's output is declared to be correct if it lies within a certain range of the checker's output. The key benefit of stochastic checkers is that the intrinsic compactness of stochastic logic leads to greatly reduced overheads. However, due to the approximate nature of stochastic circuits, errors that cause the output to be within a certain range of the correct value may not be detected (missed coverage). In addition, some correct outputs may be incorrectly flagged as erroneous (false positives). To limit the number of missed errors and false positives, we propose a technique that uses input permuted partial replicas of the stochastic logic to improve accuracy without greatly increasing the overheads. We also address the challenge of error detection latency (due to the bit-serial nature of stochastic logic) through progressive checking policies that produce an early decision based on a prefix of the checker's output bitstream. We evaluate stochastic checkers on hardware implementations of a suite of error-resilient applications, and demonstrate that they can lead to greatly reduced overheads (29.5% area and 21.5% power, on average) compared to traditional fault tolerance techniques, while achieving very high coverage (average of 99.5%) and very low false positives (average of 0.1%).","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129261597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells 基于单层和双层二维过渡金属二硫化物(TMD)的逻辑电路和6T SRAM电池的基准测试

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934630

Chang-Hung Yu, P. Su, C. Chuang

{"title":"Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells","authors":"Chang-Hung Yu, P. Su, C. Chuang","doi":"10.1145/2934583.2934630","DOIUrl":"https://doi.org/10.1145/2934583.2934630","url":null,"abstract":"We evaluate and benchmark the performance of logic circuits and stability/performance of 6T SRAM cells using monolayer and bilayer TMD devices based on ITRS 2028 (5.9nm) technology node. For the performance benchmarking of logic circuits, the tradeoff between electrostatic integrity (monolayer favored) and carrier mobility (bilayer favored), and the issues regarding the uncertainties in the mobility ratio and source/drain series resistance, the underlap device design, and the off-current spec., etc. are comprehensively addressed. In the evaluation of SRAM cells, the cell immunity to random variations is focused. Besides, the impact of high RSD of TMD materials on RSNM variability is also investigated. The source/drain underlap design is shown to alleviate the larger variability of bilayer SRAM cells. Finally, with superior electrostatics and immunity to random variations, the monolayer TMD devices are favored for low-power logic and SRAM applications; while the bilayer devices, with higher carrier mobility, are more suitable for high-performance logic and SRAM applications.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129854406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Session details: Managing Energy in Wearable Devices 会议细节:可穿戴设备中的能源管理

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/3256012

A. Khajeh, Jishen Zhao

引用次数: 0

Dynamic Approximation with Feedback Control for Energy-Efficient Recurrent Neural Network Hardware 基于反馈控制的节能递归神经网络硬件动态逼近

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934626

J. Kung, Duckhwan Kim, S. Mukhopadhyay

引用次数: 16

DeLight: Adding Energy Dimension To Deep Neural Networks 喜悦:为深度神经网络添加能量维度

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934599

B. Rouhani, Azalia Mirhoseini, F. Koushanfar

{"title":"DeLight: Adding Energy Dimension To Deep Neural Networks","authors":"B. Rouhani, Azalia Mirhoseini, F. Koushanfar","doi":"10.1145/2934583.2934599","DOIUrl":"https://doi.org/10.1145/2934583.2934599","url":null,"abstract":"Physical viability, in particular energy efficiency, is a key challenge in realizing the true potential of Deep Neural Networks (DNNs). In this paper, we aim to incorporate the energy dimension as a design parameter in the higher-level hierarchy of DNN training and execution to optimize for the energy resources and constraints. We use energy characterization to bound the network size in accordance to the pertinent physical resources. An automated customization methodology is proposed to adaptively conform the DNN configurations to the underlying hardware characteristics while minimally affecting the inference accuracy. The key to our approach is a new context and resource aware projection of data to a lower-dimensional embedding by which learning the correlation between data samples requires significantly smaller number of neurons. We leverage the performance gain achieved as a result of the data projection to enable the training of different DNN architectures which can be aggregated together to further boost the inference accuracy. Accompanying APIs are provided to facilitate rapid prototyping of an arbitrary DNN application customized to the underlying platform. Proof-of-concept evaluations for deployment of different visual, audio, and smart-sensing benchmarks demonstrate up to 100-fold energy improvement compared to the prior-art DL solutions.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115185963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47