Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization

Near threshold computing (NTC) has the potential to reduce the energy consumption by orders of magnitude. However, NTC designs suffer from a higher sensitivity to process variation and substantial performance degradation. In NTC, process variation affects the delays of different pipeline stages significantly, resulting in energy-inefficient designs. In this paper, we propose an energy-efficient variation-aware processor pipeline optimization, in which the pipeline stages are balanced by considering the impact of process variation during earlier design phases. This can lead to a well-balanced design and significant improvement in energy-efficiency. For this purpose, we employ an iterative variation-aware synthesis flow in which the synthesis tool is provided with variation information. Since the impact of process variation is considered during synthesis, our technique can improve the energy-efficiency by avoiding pessimistic guard band. Simulation results show that our technique can improve the energy-efficiency of OpenSPARC and FabScalar cores by 55% and 85%, respectively.