Proceedings of the 2016 International Symposium on Low Power Electronics and Design最新文献_第3页

A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional Computing 基于脑启发超维计算的鲁棒节能分类器

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934624

Abbas Rahimi, P. Kanerva, J. Rabaey

引用次数: 185

Session details: Low Power Design Methodologies 会议细节:低功耗设计方法

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/3256020

A. Fahim

引用次数: 0

On Effective and Efficient Quality Management for Approximate Computing 关于近似计算的有效和高效质量管理

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934608

Ting Wang, Qian Zhang, N. Kim, Q. Xu

{"title":"On Effective and Efficient Quality Management for Approximate Computing","authors":"Ting Wang, Qian Zhang, N. Kim, Q. Xu","doi":"10.1145/2934583.2934608","DOIUrl":"https://doi.org/10.1145/2934583.2934608","url":null,"abstract":"Approximate computing, where computation quality is traded off for better performance and/or energy savings, has gained significant tractions from both academia and industry. With approximate computing, we expect to obtain acceptable results, but how do we make sure the quality of the final results are acceptable? This challenging problem remains largely unexplored. In this paper, we propose an effective and efficient quality management framework to achieve controlled quality-efficiency tradeoffs. To be specific, at the offline stage, our solution automatically selects an appropriate approximator configuration considering rollback recovery for large occasional errors with minimum cost under the target quality requirement. Then during the online execution, our framework judiciously determines when and how to rollback, which is achieved with cost-effective yet accurate quality predictors that synergistically combine the outputs of several basic light-weight predictors. Experimental results demonstrate that our proposed solution can achieve 11% to 23% energy savings compared to existing solutions under the target quality requirement.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130361964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

SATS: An Ultra-Low Power Time Synchronization for Solar Energy Harvesting WSNs SATS:太阳能收集WSNs的超低功率时间同步

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934601

Tongda Wu, Yongpan Liu, Hehe Li, C. Xue, H. Lee, Huazhong Yang

引用次数: 3

OS-based Resource Accounting for Asynchronous Resource Use in Mobile Systems 基于操作系统的移动系统异步资源使用资源计费

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934639

Farshad Ghanei, Pranav Tipnis, Kyle Marcus, Karthik Dantu, Steven Y. Ko, Lukasz Ziarek

{"title":"OS-based Resource Accounting for Asynchronous Resource Use in Mobile Systems","authors":"Farshad Ghanei, Pranav Tipnis, Kyle Marcus, Karthik Dantu, Steven Y. Ko, Lukasz Ziarek","doi":"10.1145/2934583.2934639","DOIUrl":"https://doi.org/10.1145/2934583.2934639","url":null,"abstract":"One essential functionality of a modern operating system is to accurately account for the resource usage of the underlying hardware. This is especially important for computing systems that operate on battery power, since energy management requires accurately attributing resource uses to processes. However, components such as sensors, actuators and specialized network interfaces are often used in an asynchronous fashion, and makes it difficult to conduct accurate resource accounting. For example, a process that makes a request to a sensor may not be running on the processor for the full duration of the resource usage; and current mechanisms of resource accounting fail to provide accurate accounting for such asynchronous uses. This paper proposes a new mechanism to accurately account for the asynchronous usage of resources in mobile systems. Our insight is that by accurately relating the user requests with kernel requests to device and corresponding device responses, we can accurately attribute resource use to the requesting process. Our prototype implemented in Linux demonstrates that we can account for the usage of asynchronous resources such as GPS and WiFi accurately.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"332 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114233958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Analysis and Design of Energy Efficient Time Domain Signal Processing 节能时域信号处理的分析与设计

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934585

Zhengyu Chen, Jie Gu

引用次数: 10

Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency 测量驱动的方法评估处理器异构选项的功率-性能效率

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934637

William J. Song, A. Buyuktosunoglu, Chen-Yong Cher, P. Bose

{"title":"Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency","authors":"William J. Song, A. Buyuktosunoglu, Chen-Yong Cher, P. Bose","doi":"10.1145/2934583.2934637","DOIUrl":"https://doi.org/10.1145/2934583.2934637","url":null,"abstract":"It is generally perceived that heterogeneous multicore processors will provide better performance and power efficiency over conventional homogeneous cores. However, heterogeneity can also be achieved within a homogeneous core design, instantiated under different voltage-frequency settings or per-core simultaneous multi-treading (SMT) modes. In this paper, we pursue an architectural study motivated by the question, \"Can we get by with a single, complex SMT-equipped core design that can operate at different voltage-frequency points? Or, is it mandatory to invest into two different core types, one complex and the other simple?\" We propose a systematic, measurement-driven methodology to evaluate processor heterogeneity options. Our analysis particularly focuses on the domain of real-time constrained embedded processors. The study is based on a direct measurement of two real processors; one that uses simple in-order cores, and another that uses complex out-of-order cores. The effect of heterogeneous core composition (consisting of complex and simple cores in the same chip) is analytically projected from measurements gleaned from the two different systems. Our analysis yields new interesting insights. When dealing with two core types without SMT enabled, true core heterogeneity does not necessarily provide better performance or power efficiency under area and power constraints. If the complex-core homogeneous processor invokes SMT, it outperforms true heterogeneity by offering 28% better power efficiency, assuming that simple cores in the heterogeneous system operate only in single-threaded mode without SMT capability. If the small cores employ SMT, true heterogeneity yields 32% better power efficiency than the homogeneous processor with SMT.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114966076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster 基于深度流水线FPGA集群的节能CNN实现

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934644

Chen Zhang, Di Wu, Jiayu Sun, Guangyu Sun, Guojie Luo, J. Cong

引用次数: 183

A Thermal-Aware Physical Space Allocation Strategy for 3D Flash Memory Storage Systems 三维闪存存储系统的热感知物理空间分配策略

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934638

Yi Wang, Mingxu Zhang, Lisha Dong, Xuan Yang

{"title":"A Thermal-Aware Physical Space Allocation Strategy for 3D Flash Memory Storage Systems","authors":"Yi Wang, Mingxu Zhang, Lisha Dong, Xuan Yang","doi":"10.1145/2934583.2934638","DOIUrl":"https://doi.org/10.1145/2934583.2934638","url":null,"abstract":"Three-dimensional (3D) flash memory stacks layers of data storage cells vertically to overcome the scaling limits in conventional planar NAND flash memory. Current 3D flash memory faces new challenges including thermal issues and complex manufacturing process. This paper presents TheraPhy, a novel thermal-aware physical space allocation strategy for three-dimensional flash memory storage systems. TheraPhy permutes the allocation of physical blocks. Consecutively accessed logical blocks are distributed to different physical locations in order to prevent the accumulation of hotspots. TheraPhy requires no changes to the file system, on-chip memory hierarchy, or hardware implementation of 3D flash memory. Based on TheraPhy, we present an address mapping strategy that is capable of determining the allocation of physical blocks based on their thermal status. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that TheraPhy can reduce the peak temperature by 15.39% with less than 1% extra erase overhead in comparison with the baseline scheme.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133576331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions 如何应对单片3D集成电路顶层的慢速晶体管:设计研究和CAD解决方案

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934643

S. Samal, D. Nayak, M. Ichihashi, S. Banna, S. Lim

{"title":"How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions","authors":"S. Samal, D. Nayak, M. Ichihashi, S. Banna, S. Lim","doi":"10.1145/2934583.2934643","DOIUrl":"https://doi.org/10.1145/2934583.2934643","url":null,"abstract":"In this paper we study the impact of low thermal budget process on design quality in monolithic 3D ICs (M3D). Specifically, we quantify how much the tier-to-tier transistor performance difference affects full-chip power and performance metrics in a foundry 14nm FinFET technology. Our study first shows that 5%, 10%, and 15% top-tier device degradation in a wire-dominated, timing-closed monolithic 3D IC design leads to 7%, 12%, and 18% full-chip timing violation, respectively. Next, we address this impact with our CAD solution named Tier-Aware M3D (TA-M3D) flow that identifies potential timing-critical paths and partitions them into the faster (bottom) tier to minimize the top-tier degradation impact. One unique challenge in timing closure in this case, is how to conduct buffering and sizing on the paths that lie entirely in the top or bottom-tier as well as those that span both tiers. Our approach handles all 3 types of paths carefully and closes timing under the given top-tier degradation assumption, while minimizing the total power consumption. Our enhanced monolithic 3D IC designs, even with 5%, 10%, and 15% slower transistors in the top-tier, still offers 26%, 24%, and 5% power savings over 2D IC, respectively. Our study also covers other types of circuits.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132627873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7