Proceedings of the 2016 International Symposium on Low Power Electronics and Design最新文献_第2页

Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design 电压可扩展设计中保持时序弹性的综合分析、建模与设计

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934584

Huanyu Wang, Geng Xie, Jie Gu

{"title":"Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design","authors":"Huanyu Wang, Geng Xie, Jie Gu","doi":"10.1145/2934583.2934584","DOIUrl":"https://doi.org/10.1145/2934583.2934584","url":null,"abstract":"Resiliency to timing violation is a crucial requirement for low power electronics operating across a wide range of supply voltages. Although many existing solutions enhance setup timing tolerance for the higher performance, an accurate modeling and design strategy for hold resiliency dealing with conflicting requirement from both high voltages and low voltages has not been established. This paper proposes a novel voltage-scalable modeling technique that leverages conventional static timing analysis and efficient statistical analysis to achieve accurate stochastic hold timing analysis. Several highly nonlinear behaviors of circuit operation are also incorporated into the proposed model to achieve a model accuracy of within 10% of spice Monte-Carlos simulation. Leveraging the proposed modeling technique, a novel hold resilience design technique is proposed to eliminate the excessive hold fixing operation for low voltage operation and its associated performance degradation at high voltage while still being compatible with conventional design closure flow. The proposed design methodology is demonstrated in a 45nm DSP processor design enabling a voltage-scalable operation from 0.35V to 0.9V eliminating more than 20,000 hold buffers as well as 23% performance degradation at high voltages due to hold fixing.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130820009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs 用于3d - cpu的电压噪声诱导DRAM软误差降低技术

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934589

Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Ankur Srivastava

引用次数: 5

Session details: Novel Technologies & Resilience Design 会议细节:新技术和弹性设计

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/3256011

Swaroop Ghosh, Tsung-Te Liu

引用次数: 0

Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques 磁攻击和热攻击对stream性能的影响及低开销缓解技术

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934614

Jaedong Jang, Swaroop Ghosh

引用次数: 9

Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper 在数据中心中实现基于fpga的加速的软件基础设施:邀请论文

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2953984

J. Cong, Muhuan Huang, P. Pan, Di Wu, Peng Zhang

引用次数: 26

Therma: Thermal-aware Run-time Thread Migration for Nanophotonic Interconnects 热:纳米光子互连的热感知运行时线程迁移

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934592

Majed Valad Beigi, G. Memik

引用次数: 8

An Energy-Efficient PUF Design: Computing While Racing 节能PUF设计:赛车时计算

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934604

Hongxiang Gu, T. Xu, M. Potkonjak

引用次数: 3

Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures 用于弹性结构的低面积、低功耗、鲁棒、高灵敏度的错误检测锁存器

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934600

Weizhe Hua, R. Tadros, P. Beerel

引用次数: 10

Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper 解析至强+ FPGA:为什么cpu和FPGA的集成会对数据中心的功耗产生影响:特邀论文

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2953983

H. Schmit, Randy Huang

引用次数: 8

Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors 优化高性能处理器合成参数的可伸缩自动调谐

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934620

M. Ziegler, Hung-Yi Liu, L. Carloni

{"title":"Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors","authors":"M. Ziegler, Hung-Yi Liu, L. Carloni","doi":"10.1145/2934583.2934620","DOIUrl":"https://doi.org/10.1145/2934583.2934620","url":null,"abstract":"Modern logic and physical synthesis tools provide numerous options and parameters that can drastically impact design quality; however, the large number of options leads to a complex design space difficult for human designers to navigate. By employing intelligent search strategies and parallel computing we can tackle this parameter tuning problem, thus automating one of the key design tasks conventionally performed by a human designer. In this paper we present a novel learning-based algorithm for synthesis parameter optimization. This new algorithm has been integrated into our existing autonomous parameter-tuning system, which was used to design multiple 22nm industrial chips and is currently being used for 14nm chips. These techniques show, on average, over 40% reduction in total negative slack and over 10% power reduction across hundreds of 14nm industrial processor macros while reducing overall human design effort. We also present a new higher-level system that manages parameter tuning of multiple designs in a scalable way. This new system addresses the needs of large design teams by prioritizing the tuning effort to maximize returns given the available compute resources.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123287530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15