Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures

Abstract

Operating at lower supply voltages to meet ever-increasing demands for power-efficiency unfortunately aggravates process, voltage, and temperature (PVT) variability. Resilient architectures have emerged as a promising way to mitigate widening worst-case margins at these voltages. In particular, timing resilient architectures use extra circuitry to detect timing violations and recover to its normal operation. The error detecting latch (EDL) is an efficient circuit that helps perform this task. This paper proposes two EDL architectures that achieve as much as 11.2% less power consumption, 20.8% less leakage, 7.8% smaller area, and 18.2% better sensitivity to glitches compared to state-of-the-art EDLs. The paper offers two different flavors trading off robustness for lower power and vice versa. The paper also proposes a comprehensive power metric encapsulating many of the various energy aspects discussed in the literature.