2019 IEEE Applied Power Electronics Conference and Exposition (APEC)最新文献_第2页

Mission Profile-based Accelerated Testing of DC-link Capacitors in Photovoltaic Inverters 基于任务剖面的光伏逆变器直流电容加速测试

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-05-24 DOI: 10.1109/APEC.2019.8721794

A. Sangwongwanich, Yanfeng Shen, A. Chub, E. Liivik, D. Vinnikov, Huai Wang, F. Blaabjerg

{"title":"Mission Profile-based Accelerated Testing of DC-link Capacitors in Photovoltaic Inverters","authors":"A. Sangwongwanich, Yanfeng Shen, A. Chub, E. Liivik, D. Vinnikov, Huai Wang, F. Blaabjerg","doi":"10.1109/APEC.2019.8721794","DOIUrl":"https://doi.org/10.1109/APEC.2019.8721794","url":null,"abstract":"The dc-link capacitor is considered as a weak component in Photovoltaic (PV) inverter system and its reliability needs to be evaluated and tested during the product development. Conventional reliability testing methods do not consider the real operating conditions (e.g., mission profile) of the dc-link capacitor during the test. Therefore, the validation of the reliability performance of the dc-link capacitor under its mission profile is still a challenge. To address this issue, a new reliability testing concept for the dc-link capacitor in PV inverters is proposed in this paper. In contrast to the conventional method, the proposed reliability testing method realizes the test profile through the modification of the original mission profile (e.g., solar irradiance and ambient temperature) in order to maintain the test condition as close to the real application as possible. A certain acceleration factor is applied to the solar irradiance amplitude and the ambient temperature level during the mission profile modification in order to increase the thermal stress of the dc-link capacitor during test, and thereby effectively reduce the testing time. The results show that the testing time can be reduced to 2.5 % of the real field operation lifetime, if the solar irradiance amplitude is increased by 20 % and the ambient temperature is elevated to 75 °C.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129938532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A Comparative Study of Failure-Tolerant Three-phase RTRUs for More Electric Aircrafts 多电动飞机三相容错rtru的比较研究

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-05-24 DOI: 10.1109/APEC.2019.8722048

Akshay Singh, Ayan Mallik, A. Khaligh

引用次数: 7

Fundamental Switching Frequency Pulse Width Modulation of Nine-Level Current-fed Multilevel Converter for Solar Application 太阳能用九电平电流多电平变换器的基频开关脉宽调制

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-05-24 DOI: 10.1109/APEC.2019.8722260

G. K, A. Rathore, D. Srinivasan, José R. Rodríguez

{"title":"Fundamental Switching Frequency Pulse Width Modulation of Nine-Level Current-fed Multilevel Converter for Solar Application","authors":"G. K, A. Rathore, D. Srinivasan, José R. Rodríguez","doi":"10.1109/APEC.2019.8722260","DOIUrl":"https://doi.org/10.1109/APEC.2019.8722260","url":null,"abstract":"The aim of this paper is to develop a real-time computational method that determines switching angles of selective harmonic elimination (SHE) for operating nine-level (9L) current-fed multilevel converter(MLC). The computation algorithm for SHE conventionally requires huge calculation time to identify switching angles of the inverter and hence a truth table based modulation is applied for operating the converter in real-time. To overcome this, a new analytical method has been proposed in this paper that minimizes the computation time to calculate the switching angles. However, these switching angles cannot be directly applied to current-fed MLCs. Unlike voltage fed converters, the current-fed converters have additional operational constraints on the modulation technique. Hence in this paper, a conversion technique has been utilized to convert the un-constraint SHE angles into constraint angles in order to operate current-fed MLCs. A low power prototype of 9L current source inverter has been set-up to experiment and validate the proposed real-time calculation method at the fundamental frequency of 50Hz.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117110221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Performance Benchmark of Bypassing Techniques for Photovoltaic Modules 光伏组件旁路技术的性能基准

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-05-24 DOI: 10.1109/APEC.2019.8722259

Kamran Ali Khan Niazi, Yongheng Yang, H. Khan, D. Sera

引用次数: 7

Two-Level Algorithm for UPQC Considering Power Electronic Converters and Transformers 考虑电力电子变换器和变压器的两级UPQC算法

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-05-24 DOI: 10.1109/APEC.2019.8722007

Jian Ye, H. Gooi, Xinan Zhang, Benfei Wang, U. Manandhar

引用次数: 9

Modulation Scheme for an Effective Increase in the Number of Levels of DC-DC Multi-Level Flying Capacitor Converters 有效提高DC-DC多级飞容变换器电平数的调制方案

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722325

Michael Halamíček, T. McRae, N. Vukadinović, A. Prodic

{"title":"Modulation Scheme for an Effective Increase in the Number of Levels of DC-DC Multi-Level Flying Capacitor Converters","authors":"Michael Halamíček, T. McRae, N. Vukadinović, A. Prodic","doi":"10.1109/APEC.2019.8722325","DOIUrl":"https://doi.org/10.1109/APEC.2019.8722325","url":null,"abstract":"This paper introduces a novel modulation scheme for dc-dc multi-level flying capacitor buck converters that effectively increases the number of converter levels. It is shown that, in general, an N-level flying capacitor converter can be split simultaneously into an $frac{{N + 2}}{2}$ and an $frac{{N + 3}}{2}$ level flying capacitor converter. This modulation scheme creates unequal differences between the flying capacitor voltages which can be used to reduce the voltage swing at the switching node and thus the size of the inductor. The voltage swing becomes equivalent to an $frac{{{N^2} + 3}}{4}$ level converter for some conversion ratios. Additionally, this modulation scheme has passive flying capacitor voltage balancing, simplifying controller design. A 5-level flying capacitor converter was modulated to create a 3,4-level converter with the effective voltage swing of a 7-level converter. The functionality of this modulation scheme was confirmed with a 24V-to-9V, 45W 5-level buck converter confirming a 35% reduction in the inductor ripple and, thus, allowing for the equivalent inductor reduction.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115480051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design and Implementation of Forced Air-cooled, 140kHz, 20kW SiC MOSFET based Vienna PFC 基于维也纳PFC的强制风冷，140kHz, 20kW SiC MOSFET的设计与实现

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721979

Siyuan Chen, Wensong Yu, Dennis Meyer

引用次数: 21

A non-isolated high step-up hybrid resonant converter based on hybrid transformer 基于混合变压器的非隔离高升压混合谐振变换器

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721927

Wenhao Xie, Yifei Zheng, Shouxian Li, Jianze Wang, Yanchao Ji, Jilai Yu

引用次数: 2

A 48-to-12 V Cascaded Resonant Switched-Capacitor Converter for Data Centers with 99% Peak Efficiency and 2500 W/in3 Power Density 用于数据中心的48 ~ 12v级联谐振开关电容变换器，峰值效率99%，功率密度2500w /in3

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721812

Zichao Ye, Y. Lei, R. Pilawa-Podgurski

引用次数: 46

In Depth Analysis of Driving Loss and Driving Power Supply Structure for SiC MOSFETs SiC mosfet驱动损耗及驱动电源结构的深入分析

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722272

Xuning Zhang, G. Sheh, I. Ji, Sujit Banerjee

{"title":"In Depth Analysis of Driving Loss and Driving Power Supply Structure for SiC MOSFETs","authors":"Xuning Zhang, G. Sheh, I. Ji, Sujit Banerjee","doi":"10.1109/APEC.2019.8722272","DOIUrl":"https://doi.org/10.1109/APEC.2019.8722272","url":null,"abstract":"This paper presents an in-depth analysis of the driving loss for SiC MOSFETs in real applications to help designer determined the power rating of proper gate driving power supplies and select proper gate resistors with enough power rating. A detailed loss estimation method is provided based on the datasheet information. Results verifies that the total driving loss power is determined by driving voltage, device total gate charge and switching frequency. The driving loss distribution analysis with the consideration of the nonlinearity of device gate capacitance is presented which indicates that the loss on turn on and turn off resistors is different, and the loss distribution is related with device working conditions. The power supply implementation for negative voltage driving is also discussed. If two separate voltage sources provide the driving power, each of them must provide real power to drive device gate. If only one voltage source provides the total driving power, a voltage divider circuit or voltage regulate circuit is needed only to provide voltage reference, there is no current through the divider or regulator. No real power is needed from the divider or regulator circuit. Experimental test results are provided to verify all the analysis.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128677473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2