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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)最新文献

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Minimum settling time voltage regulation of single-phase PFC converters 单相PFC变换器的最小稳定时间电压调节
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957702
P. Ninkovic, Ž. Janda
{"title":"Minimum settling time voltage regulation of single-phase PFC converters","authors":"P. Ninkovic, Ž. Janda","doi":"10.1109/ICECS.2001.957702","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957702","url":null,"abstract":"This paper presents a method for extremely fast output voltage regulation in the single-phase power-factor-correction circuits based on a single-switch boost converter. The problem associated with conventional control circuit is recognized, one appropriate solution with optimal filter is suggested and then the regulator for the fastest possible response is determined. The design guidelines are presented. The experiment with 220V/700W converter is performed and very good results are obtained in accordance with the theory.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125699317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Counting up of linear lumped parameter systems and their unified representation 线性集总参数系统的计数及其统一表示
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957602
T. Yamawaki
{"title":"Counting up of linear lumped parameter systems and their unified representation","authors":"T. Yamawaki","doi":"10.1109/ICECS.2001.957602","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957602","url":null,"abstract":"This paper discloses a lack of general theory for lumped parameter systems, containing continuous time systems, discrete time systems, systems with time delay, and sampled data systems. Also it provides a unified basis for linear systems of lumped parameters. The basis includes signal spaces mapped with real time functions and delta function series, operator notations of integral and time delay, modified sampled data, a new method to classify linear systems, and a unified representation of six classes of linear systems of time-invariant lumped parameters. For demonstrative examples of modified sampled data, the conventional sampled data system models of interpolating circuits are revised due to false counterexamples of Shannon's sampling theorem.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120966833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog CMOS implementation of feature detection operators for automatic real-time optical character recognition systems 模拟CMOS实现的特征检测算子，用于自动实时光学字符识别系统
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957689
D. Caviglia, M. Tosato, Marco Mazzucco, G. M. Bo, M. Valle
{"title":"Analog CMOS implementation of feature detection operators for automatic real-time optical character recognition systems","authors":"D. Caviglia, M. Tosato, Marco Mazzucco, G. M. Bo, M. Valle","doi":"10.1109/ICECS.2001.957689","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957689","url":null,"abstract":"Low-power, high efficiency, small size and real-time optical character recognition (OCR) systems can benefit from the analog VLSI implementation of (at least) some of their constituting modules. The reference architecture usually consists of a feature detection and extraction block (FE) directly interfaced to the on-chip CMOS sensor, and of a classifier. The FE purpose is to reduce the redundancy of information in handwritten character images prior to feeding the classifier. The analog circuit architecture of an FE block and its circuit implementation are presented and discussed. It can be used for both segmented and nonsegmented strings of characters. The circuit implementation is based on weak-inversion operated circuits. The real-time speed, low power and small size are achieved through careful power-speed tradeoff optimization at both architectural and circuit levels.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116248234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling 通过应用非零时钟偏差调度在工业电路上提高速度的演示
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957650
D. Velenis, K. Tang, I. Kourtev, V. Adler, F. Baez, E. Friedman
{"title":"Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling","authors":"D. Velenis, K. Tang, I. Kourtev, V. Adler, F. Baez, E. Friedman","doi":"10.1109/ICECS.2001.957650","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957650","url":null,"abstract":"A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown that non-zero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a non-zero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays by replacing clock buffers from predesigned cell libraries. Timing margin improvements of up to 18% are achieved through the application of non-zero clock skew scheduling in certain functional blocks of an industrial high performance microprocessor.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116263476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel CMOS charge-pump circuit with positive feedback for PLL applications 一种用于锁相环的新型正反馈CMOS电荷泵电路
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957751
E. Juárez-Hernández, A. Díaz-Sánchez
{"title":"A novel CMOS charge-pump circuit with positive feedback for PLL applications","authors":"E. Juárez-Hernández, A. Díaz-Sánchez","doi":"10.1109/ICECS.2001.957751","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957751","url":null,"abstract":"The design and simulation of a novel CMOS charge-pump circuit for PLL applications is presented. The proposed circuit makes use of positive feedback to increase the switching speed and current reuse to minimize the power consumption. H-SPICE simulations for a 0.35 /spl mu/m AMS technology show the potential of the proposed structure for high-frequency applications.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122515930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Design of a CMOS fully differential switched-opamp for SC circuits at very low power supply voltages 用于极低电源电压下SC电路的CMOS全差分开关运放的设计
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957510
Jesús Arias Álvarez, L. Quintanilla, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez, A. Rueda
{"title":"Design of a CMOS fully differential switched-opamp for SC circuits at very low power supply voltages","authors":"Jesús Arias Álvarez, L. Quintanilla, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez, A. Rueda","doi":"10.1109/ICECS.2001.957510","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957510","url":null,"abstract":"This paper presents a fully differential opamp design based on the switched-opamp approach. The common mode feedback of the proposed opamp only works on the output stage in order to allow a fast turn-on. The opamp was designed in a 0.35 /spl mu/m CMOS technology and is able to operate from a single 1 V supply.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122790991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
New approach to analog filters and group delay equaliser transfer function design 模拟滤波器和群延迟均衡器传递函数设计的新方法
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957704
J. Vondras, P. Martínek
{"title":"New approach to analog filters and group delay equaliser transfer function design","authors":"J. Vondras, P. Martínek","doi":"10.1109/ICECS.2001.957704","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957704","url":null,"abstract":"The starting point for filters and group delay equalisers design is the appropriate solution of the approximation problem. Through the presented technique is possible to design a transfer function standard even no standard filters with respect to their poles and zeros quality and group delay responses. The technique was also used for transfer function design of group delay equaliser. In this case there were prescribed requirements on group delay response and quality of poles and zeros as well. To solve these large constraint problems, modifying Differential Evolution (DE) is used, as an effective way for penalty function minimisation.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122900790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On-line digital correction of the harmonic distortion in analog-to-digital converters 模数转换器谐波失真的在线数字校正
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957604
U. Eduri, F. Maloberti
{"title":"On-line digital correction of the harmonic distortion in analog-to-digital converters","authors":"U. Eduri, F. Maloberti","doi":"10.1109/ICECS.2001.957604","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957604","url":null,"abstract":"A digital calibration technique for the on-line (real-time) correction of the Integral Nonlinearity (INL) in any Analog-to-Digital Converter (ADC) has been presented in this paper. MATLAB simulations substantiating the technique achieved around 20 dB improvement on a modeled 12-bit ADC with an initial Spurious-Free Dynamic Range of 80 dBFS. As a bonus, this technique can also correct for the offset error. The price paid for these benefits is the inclusion of an identical extra ADC, and some additional DSP circuitry.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131284899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fault tolerant unicast routing algorithm based on parallel branching method for faulty hypercube 基于并行分支方法的故障超立方体容错单播路由算法
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957686
S. Günes, N. Yilmaz, E. Yaldiz
{"title":"Fault tolerant unicast routing algorithm based on parallel branching method for faulty hypercube","authors":"S. Günes, N. Yilmaz, E. Yaldiz","doi":"10.1109/ICECS.2001.957686","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957686","url":null,"abstract":"In this study, a unicast routing algorithm based on the parallel branching method has been developed for a faulty hypercube parallel processing system. The developed method has been compared with the cube algebra method developed by us and with studies in the literature related to this subject. With the developed routing algorithm, the routing from the source node to the destination node is fulfilled in the available minimal step without any restriction on the number of faulty nodes. In the algorithm, the system with circuit switching has been considered, and the obtained results have been visually simulated by using the developed hypercube routing simulation program. The performance of the simulator has been evaluated by using a comparison of the number of fulfilled processes versus the number of faulty nodes for the two methods developed by us.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131527299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI implementation of CRC-32 for 10 Gigabit Ethernet 用于10千兆以太网的CRC-32的VLSI实现
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957433
T. Henriksson, H. Eriksson, U. Nordqvist, P. Larsson-Edefors, Dake Liu
{"title":"VLSI implementation of CRC-32 for 10 Gigabit Ethernet","authors":"T. Henriksson, H. Eriksson, U. Nordqvist, P. Larsson-Edefors, Dake Liu","doi":"10.1109/ICECS.2001.957433","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957433","url":null,"abstract":"For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131542709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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