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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)最新文献

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Design verification of an 18-million-transistor digital television and media processor chip 一个1800万晶体管数字电视和媒体处理器芯片的设计验证
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957498
S. Dutta
{"title":"Design verification of an 18-million-transistor digital television and media processor chip","authors":"S. Dutta","doi":"10.1109/ICECS.2001.957498","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957498","url":null,"abstract":"This paper describes the verification methodology that has been followed in the design of NX-2700 - a digital television and media processor chip from Philips Semiconductors. Targeted at the digital television (DTV) markets, the NX-2700 processor not only supports all of the eighteen ATSC DTV formats, from standard-definition to wide-angle, high-definition video, but has also the power to handle video and audio source decoding (high-level MPEG-2, AC-3 and ProLogic audio, closed captioning, etc.). Featuring a programmable, general-purpose VLIW CPU core (that implements many non-trivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system), NX-2700 is a true example of a system-on-a-chip; the CPU core, aided by an array of peripheral devices (multimedia co-processors and input-output units) and high-performance buses, facilitates concurrent processing of audio, video, graphics, and communication-data.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130892761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast characterization of RTL power macromodels RTL功率宏模型的快速表征
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957521
M. Anton, I. Colonescu, E. Macii, M. Poncino
{"title":"Fast characterization of RTL power macromodels","authors":"M. Anton, I. Colonescu, E. Macii, M. Poncino","doi":"10.1109/ICECS.2001.957521","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957521","url":null,"abstract":"In this work, we propose the equation table, a new register-transfer level (RTL) power macromodel that combines the features of equation-based and of table-based approaches in order to reduce the number of low-level simulations required during the characterization phase. The equation table model uses the information collected during characterization more constructively with respect to other state-of-the-art power models. This new model allows to reduce the time involved in the model construction by a factor of up to 8.6 times with respect to the conventional models, with similar accuracy and smaller amount of model storage memory.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130997940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Windows in a non-autonomous circuit with symmetry 具有对称性的非自治电路中的窗口
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957462
T. Miyoshi, M. Sekikawa, Taisuke Sato, N. Inaba, Y. Nishio
{"title":"Windows in a non-autonomous circuit with symmetry","authors":"T. Miyoshi, M. Sekikawa, Taisuke Sato, N. Inaba, Y. Nishio","doi":"10.1109/ICECS.2001.957462","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957462","url":null,"abstract":"A symmetric structure exists in many chaos-generating circuits. In those circuits, interesting bifurcation phenomena based on the symmetry of circuits, such as symmetry recovery, symmetry breaking, etc., are observed. In this study, two types of interesting windows are observed in a circuit with symmetry which we propose. This circuit has a pair of diodes. We consider the case in which the pair of diodes operates as a pair of ideal switches. In this case, the Poincare/spl acute/ map can be derived rigorously as a one-dimensional map. We prove that a countably infinite number of two types of windows are generated alternately by applying the theorem written in a previous paper (Nishio et al, IEEE Trans. Circuits Syst., vol. 37, no. 4, pp. 473-487, 1990) to the one-dimensional map.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125405320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An area-efficient interpolation filter using block structure 采用块结构的面积高效插值滤波器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957624
Kyu Ha Lee, D. Youn, Chungyong Lee
{"title":"An area-efficient interpolation filter using block structure","authors":"Kyu Ha Lee, D. Youn, Chungyong Lee","doi":"10.1109/ICECS.2001.957624","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957624","url":null,"abstract":"A new interpolation filtering architecture using block structure and look-up table (LUT) is proposed. Using parallel processing inherited from block structure, the filtering rate and the power consumption are lowered, which makes the proposed architecture appropriate for the modulator in a mobile communication system. Also, applying the symmetric property of filter coefficients, the LUT size and memory requirement are reduced. The proposed filter architecture is generalized by reconstructing the LUT. As a design result, comparison with the prior LUT-based architectures showed that the proposed filter architecture is more area-efficient.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125570554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parameter identification of a DC motor: an experimental approach 直流电机参数辨识的实验方法
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957638
S. Saab, Raed Abi Kaed-Bey
{"title":"Parameter identification of a DC motor: an experimental approach","authors":"S. Saab, Raed Abi Kaed-Bey","doi":"10.1109/ICECS.2001.957638","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957638","url":null,"abstract":"The main goal of this paper is to estimate the parameters of a DC motor experimentally employing discrete measurements of an integrated dynamometer. The parameters under consideration are the motor armature-winding resistance and inductance, back e.m.f. constant, motor torque constant, moment of inertia, and the viscous friction. The dynamometer outputs are the discrete measurements of the armature current, angular velocity, armature voltage (system input), and the torque developed by the motor. In this paper parameter identification of a DC motor, employing the least-squares algorithm, is implemented without the use of a D/A converter and a power amplifier. In particular, the armature voltage is generated using a prime mover and a synchronous generator. The data acquisition system is composed of the existing dynamometer data acquisition coupled with special software resulting in collecting different measurements automatically at a desired fixed time interval. A Kalman filter is also implemented, as a state observer, to estimate the angular acceleration and the derivative of the armature current. In addition, to improve the overall identification performance, the DC parameters were first estimated by decoupling the AC parameters using a DC input signal. Subsequently, the estimated DC parameters are then used to identify the AC parameters. Experimental results are included to illustrate the efficiency of the proposed system.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126220588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
SPICE model for the single electron tunnel junction 单电子隧道结的SPICE模型
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957487
R. V. D. Haar, R. H. Klunder, J. Hoekstra
{"title":"SPICE model for the single electron tunnel junction","authors":"R. V. D. Haar, R. H. Klunder, J. Hoekstra","doi":"10.1109/ICECS.2001.957487","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957487","url":null,"abstract":"In this paper a SPICE model for a single electron tunnel junction is given. The model is derived from a new formulation of the tunnel condition based on voltages over the tunnel junctions. To validate the model an electron box is simulated.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126427279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Power reduction for multimedia applications through data-reuse memory exploration 通过数据重用内存探索来降低多媒体应用程序的功耗
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957675
M. Kougia, A. Chatzigeorgiou, S. Nikolaidis
{"title":"Power reduction for multimedia applications through data-reuse memory exploration","authors":"M. Kougia, A. Chatzigeorgiou, S. Nikolaidis","doi":"10.1109/ICECS.2001.957675","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957675","url":null,"abstract":"Power consumption of multimedia applications executing on embedded cores is heavily dependent on data transfers between system memory and processing units. In this paper, a power optimizing methodology based on data-reuse decisions and the development of a custom memory hierarchy is extended in order to determine the optimal solution in a rapid and reliable way. Data-reuse transformations are applied on a typical motion estimation algorithm in order to reduce the data-related power consumption by moving background memory accesses to smaller foreground memories, which are less power costly. Fast exploration of the design space is achieved by extracting analytical expressions for the number of accesses to data and instruction memories.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A proof of the non-existence of universal nonlinearities for blind signal separation 盲信号分离中普遍非线性不存在的证明
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957445
H. Mathis
{"title":"A proof of the non-existence of universal nonlinearities for blind signal separation","authors":"H. Mathis","doi":"10.1109/ICECS.2001.957445","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957445","url":null,"abstract":"The universally applicable nonlinearity for the blind separation of arbitrary source densities is one of the ultimate goals in blind signal processing. This paper provides a proof that such a single, universal nonlinearity for the separation of all non-Gaussian signals cannot exist.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123109964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A framework for a wavelet-based high level environment 一个基于小波的高级环境框架
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957771
M. Nibouche, A. Bouridane, O. Nibouche
{"title":"A framework for a wavelet-based high level environment","authors":"M. Nibouche, A. Bouridane, O. Nibouche","doi":"10.1109/ICECS.2001.957771","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957771","url":null,"abstract":"Although FPGA technology offers the potential of designing high performance systems at low cost for a wide range of applications, its programming model is prohibitively low level requiring either a dedicated FPGA-experienced programmer or basics digital design knowledge. To allow a signal/image processing end-user to benefit from these kind of devices, the level of design abstraction needs to be raised, even beyond a hardware description language level (e.g. VHDL). This approach will help the application developer to focus on signal/image processing algorithms rather than on tow-level designs and implementations. This paper aims to present a framework for a wavelet-based high level environment. The proposed approach will help the end-user to generate FPGA configurations for DWT at a highest level without any knowledge of the low-level design styles and architectures.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"120 22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126317070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new class of Smith predictors for network congestion control 一类用于网络拥塞控制的Smith预测器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957568
P. Bauer, M. Sichitiu, Russ Ernst, K. Premaratne
{"title":"A new class of Smith predictors for network congestion control","authors":"P. Bauer, M. Sichitiu, Russ Ernst, K. Premaratne","doi":"10.1109/ICECS.2001.957568","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957568","url":null,"abstract":"A new class of time-variant Smith predictors for buffer set point control over communication networks is proposed. The new Smith predictor uses two different types of time-variant network delay models, i.e. the forward delay (modeling delay effects on the data stream) and the return delay (modeling delay effects on the buffer occupancy information.) The proposed control scheme tracks the desired buffer level, even under large delay uncertainties, abrupt delay changes and additional disturbances such as unknown buffer depletion rates. The question of stability of the resulting system will also be analyzed. Applications of the proposed scheme range from load balancing in distributed computing to congestion control in WAN networks.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"10 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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