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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)最新文献

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Maximizing bandwidth in CCII for wireless optical applications 最大化无线光学应用的CCII带宽
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957409
L. N. Alves, R. Aguiar
{"title":"Maximizing bandwidth in CCII for wireless optical applications","authors":"L. N. Alves, R. Aguiar","doi":"10.1109/ICECS.2001.957409","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957409","url":null,"abstract":"This paper discusses bandwidth problems associated with the usage of second-generation current conveyors in wireless optical systems, and presents a new current amplifier with wide bandwidth and large input dynamic range, developed for Fast Ethernet wireless applications. This current amplifier is used to interconnect low cost photodetectors (with large intrinsic capacitance) with transimpedance amplifiers, overcoming typical bandwidth limitations imposed by the input transducers. This current adaptation concept has proved to be adequate for increasing both bandwidth and dynamic range of traditional optical interfaces. The proposed current amplifier architecture is based on a CCII with reduced input impedance and achieves, for a 10 pF input photodetector, a maximum gain of 18 dB with a 130 MHz bandwidth, with a noise floor of 9.2 pA//spl radic/Hz. The expected input dynamic range is larger than 65 dB.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124028860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 /spl mu/m CMOS using self calibration and low power techniques 采用自校准和低功耗技术，在0.6 /spl mu/m CMOS中实现16位200 kS/s的连续近似A/D转换器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957609
H. Neubauer, T. Desel, J. Hauer
{"title":"A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 /spl mu/m CMOS using self calibration and low power techniques","authors":"H. Neubauer, T. Desel, J. Hauer","doi":"10.1109/ICECS.2001.957609","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957609","url":null,"abstract":"A low power (6.8 mW) 5 V analog 2.7 V digital 16 bit 200 kS/s charge redistribution self calibrating successive approximation (SA) analog/digital converter (ADC) is presented. The device is implemented in a 0.6 /spl mu/m CMOS technology with 2 mm/sup 2/ active area. This multi purpose ADC macro is intended to be integrated with digital signal processing on ASICs. The SA principle permits input multiplexing and sampling at discrete times.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129499855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
IC design automation from circuit level optimization to retargetable layout 从电路级优化到可重新定位布局的集成电路设计自动化
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957682
Xu Jingnan, J. Serras, M. Oliveira, R. Belo, M. Bugalho, J. Vital, N. Horta, J. Franca
{"title":"IC design automation from circuit level optimization to retargetable layout","authors":"Xu Jingnan, J. Serras, M. Oliveira, R. Belo, M. Bugalho, J. Vital, N. Horta, J. Franca","doi":"10.1109/ICECS.2001.957682","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957682","url":null,"abstract":"This paper describes a new analog and mixed-signal IC design automation environment including both multilevel optimization and layout generation based on retargeting methodologies. The circuit/system level optimization is achieved by applying a simulated annealing technique together with heuristic based rules, for constraint generation, to parametrized circuit descriptions. The layout generation is attained by automatically applying the sized schematic to reusable physical layouts of analog and mixed-signal blocks, built based on high-functionality pCells which are fully independent from technologies. The design automation methodology is illustrated with practical examples.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129877835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A general class of passive macromodels for efficient sensitivity analysis of high-speed distributed interconnects with nonlinear terminations 一类具有非线性终端的高速分布式互连的有效灵敏度分析的无源宏观模型
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957618
A. Dounavis, R. Achar, M. Nakhla
{"title":"A general class of passive macromodels for efficient sensitivity analysis of high-speed distributed interconnects with nonlinear terminations","authors":"A. Dounavis, R. Achar, M. Nakhla","doi":"10.1109/ICECS.2001.957618","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957618","url":null,"abstract":"A general class of passive macromodelling algorithm for multiport distributed interconnects is presented. A new theorem is described which specifies sufficient conditions for matrix-rational approximation of exponential functions in order to generate a passive macromodel. Also an efficient approach for sensitivity analysis of lossy multiconductor transmission lines in the presence of nonlinear terminations is described.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128196956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-voltage low-power adaptive biased high-efficiency integrated amplifiers 低电压低功率自适应偏置高效集成放大器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957506
G. Ferri
{"title":"Low-voltage low-power adaptive biased high-efficiency integrated amplifiers","authors":"G. Ferri","doi":"10.1109/ICECS.2001.957506","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957506","url":null,"abstract":"The principle and application of a novel adaptive biasing topology which reduce the stand-by power dissipation without affecting the transient performance of low-power amplifiers and buffers is presented. The basic adaptive circuit gives a current dependent on the applied input differential voltage. The differential sensitivity can be improved by introducing a very small biasing current, to compensate transistor threshold voltage, whose value can be set according to the transient performance constraints. The proposed topology, in both bipolar and CMOS technologies, can be utilized in the design of high-efficiency low-voltage low-power operational amplifiers, for the biasing of both the input stage (to increase dynamically the input source current) and the output stage (to control and limit the output current). The designed amplifiers show a very good behaviour, in terms of efficiency factor, when compared with other adaptive circuits in literature. Simulation results and measurements on a chip prototype are finally presented.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128273094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Phase error determination in GMSK modulated fractional-N PLL GMSK调制分数n锁相环的相位误差测定
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957662
L. Camino, S. Ramet, J. Bégueret, Y. Deval, P. Fouillat
{"title":"Phase error determination in GMSK modulated fractional-N PLL","authors":"L. Camino, S. Ramet, J. Bégueret, Y. Deval, P. Fouillat","doi":"10.1109/ICECS.2001.957662","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957662","url":null,"abstract":"Phase error contributors in a GMSK modulated fractional-N synthesizer are defined : the impulse response length and the oversampling ratio of the Gaussian filter, and the order and resolution of the /spl Sigma//spl utri/ converter. A method to optimise them is presented.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129653795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Architectural synthesis of digital signal processing applications dedicated to submicron technologies 建筑合成数字信号处理应用专用于亚微米技术
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957799
E. Casseau, C. Jégo, E. Martin
{"title":"Architectural synthesis of digital signal processing applications dedicated to submicron technologies","authors":"E. Casseau, C. Jégo, E. Martin","doi":"10.1109/ICECS.2001.957799","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957799","url":null,"abstract":"Architectural synthesis is an efficient design process that reduces the gap between algorithms and architectures by raising the abstraction level. However, this process currently does not take the VLSI circuit interconnection cost into account whereas this cost becomes predominant using submicron technologies. In this paper, an interconnection cost analysis at the behavioural level is performed in order to provide rapid prototyping results and to direct the synthesis process with additional path constraints. Results are presented showing the interest of this approach.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125671565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Conditional techniques for low power consumption flip-flops 低功耗人字拖的条件技术
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957596
N. Nedovic, M. Aleksic, V. Oklobdzija
{"title":"Conditional techniques for low power consumption flip-flops","authors":"N. Nedovic, M. Aleksic, V. Oklobdzija","doi":"10.1109/ICECS.2001.957596","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957596","url":null,"abstract":"Conditional capture and conditional precharge techniques for high-performance flip-flops are reviewed in terms of power and delay. It is found that application of conditional techniques can improve energy-delay product for up to 14% for 50% input activity and save more than 50% in power consumption for quiet input. This property makes conditional methods suitable for high-performance VLSI systems.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130713743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Technology tradeoffs in the design of high performance analog to digital converters 高性能模数转换器设计中的技术权衡
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957646
E. Soenen
{"title":"Technology tradeoffs in the design of high performance analog to digital converters","authors":"E. Soenen","doi":"10.1109/ICECS.2001.957646","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957646","url":null,"abstract":"A variety of communications systems benefit from the use of high performance data converters. This is the case for digital radio receivers used in cellular telephone base stations and wireless broadband applications. This paper investigates the key technology trade-offs for analog to digital converters.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130732853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The mechanical and control system design of a dexterous robotic gripper 一种灵巧机械手的机械与控制系统设计
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957430
C. Seguna, M. Saliba
{"title":"The mechanical and control system design of a dexterous robotic gripper","authors":"C. Seguna, M. Saliba","doi":"10.1109/ICECS.2001.957430","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957430","url":null,"abstract":"The design and development of dexterous robotic end effectors has been an active research area for a long while. This paper reviews the design and construction of a versatile robotic gripper used to grasp objects of arbitrary shape, size and weight. This is achieved through a mechanical design that incorporates multiple fingers and multiple joints per finger, through the installation of proximity and force sensors on the gripper, and through the employment of an innovative and practical control system architecture for the gripper components. The gripper is installed on a standard six degree-of-freedom industrial robot, and the gripper and robot control programs are integrated in a manner that allows easy application of the gripper in an industrial pick-and-place operation where the characteristics of the object can vary or are unknown.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132015452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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