Analog CMOS implementation of feature detection operators for automatic real-time optical character recognition systems

Abstract

Low-power, high efficiency, small size and real-time optical character recognition (OCR) systems can benefit from the analog VLSI implementation of (at least) some of their constituting modules. The reference architecture usually consists of a feature detection and extraction block (FE) directly interfaced to the on-chip CMOS sensor, and of a classifier. The FE purpose is to reduce the redundancy of information in handwritten character images prior to feeding the classifier. The analog circuit architecture of an FE block and its circuit implementation are presented and discussed. It can be used for both segmented and nonsegmented strings of characters. The circuit implementation is based on weak-inversion operated circuits. The real-time speed, low power and small size are achieved through careful power-speed tradeoff optimization at both architectural and circuit levels.