2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)最新文献_第9页

Co-design and Signal-Power Integrity/EMI Co-analysis of a Switchable High-speed Inter-Chiplet Serial Link on an Active Interposer 主动式中介器上可切换高速芯片间串行链路的协同设计和信号功率完整性/EMI协同分析

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00214

M. Miao, Xiaolong Duan, Liang Sun, Tao Li, Shiliang Zhu, Zhuanzhuan Zhang, Jin Li, Danya Zhang, Hao Wen, Xuena Liu, Zhensong Li

{"title":"Co-design and Signal-Power Integrity/EMI Co-analysis of a Switchable High-speed Inter-Chiplet Serial Link on an Active Interposer","authors":"M. Miao, Xiaolong Duan, Liang Sun, Tao Li, Shiliang Zhu, Zhuanzhuan Zhang, Jin Li, Danya Zhang, Hao Wen, Xuena Liu, Zhensong Li","doi":"10.1109/ectc51906.2022.00214","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00214","url":null,"abstract":"This paper proposes a chiplet-based domain specific architecture (DSA) module on active interposer for convolutions in various scenarios. By constructing an integral development frame, the I/O and inter-chiplet links behaviors together with signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) issues can be co-considered and co-analyzed in the early phases, facilitating efficient implementation of heterogeneous integration. Additionally, the proposed solution takes advantage of the flexibility of a novel network-on-chip (NoC) switching fabric for inter-chiplet data exchange and versatile auxiliary circuitry enabled by an active interposer, to enhance its performance and extend the scope of application. The design and analysis results are shown, as well as associated options and potentials of the development frame. Up to now, the prototype chip samples for the switching fabric has been delivered by foundry; detailed physical design and assembly of the DSA module with off-the-shell dies and cost- effective Si interposer solution are under way.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Fabrication and Characterization of Nanoporous Gold (NPG) Interconnects for Wafer Level Packaging 晶圆级封装用纳米孔金互连的制备与表征

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00143

L. Dietrich, H. Oppermann, C. Lopper, P. Mackowiak

{"title":"Fabrication and Characterization of Nanoporous Gold (NPG) Interconnects for Wafer Level Packaging","authors":"L. Dietrich, H. Oppermann, C. Lopper, P. Mackowiak","doi":"10.1109/ectc51906.2022.00143","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00143","url":null,"abstract":"A novel bumping and bonding technology using sponge-like gold depots with nanometer-scale skeleton construction has been developed and verified. The nanoporous gold (NPG) is formed up by selective etching the silver content from silver/gold alloys, which have been previously electrodeposited on lithographically patterned wafers. Due to the high resolution of the used photoresist systems, highest I/O densities and smallest bump sizes down to 1 μm are achieved. The desired alloy composition is adjustable in a wide range by adequate choice of the metal ion concentration in the electrolyte and by adaption of the deposition rate. The final porosity of the gold can be adjusted by sufficient choice of the etching conditions, and a final coarsening of the NPG texture can be achieved by thermal treatment prior to the bonding process. Thermal as well as mechanical tests were performed to get statements about the characteristics of the skeleton substructure and the reliability of the NPG interconnection. Exemplarily, some thermocompression (TC) bonding results are presented with focus on the NPG interconnect formation.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130044461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications 一种适用于高性能2.2D结构下填充成型工艺的新型等效模型

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00090

Yu Liang, Chia-Peng Sun, Chih Chung Hsu, D. Hu, E. Chen, J. Lee

{"title":"A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications","authors":"Yu Liang, Chia-Peng Sun, Chih Chung Hsu, D. Hu, E. Chen, J. Lee","doi":"10.1109/ectc51906.2022.00090","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00090","url":null,"abstract":"A novel methodology of 3D CAE modeling of capillary underfill of multi-chip packages with a large number of micro bumps is employed in this study. The capillary underfill flow is mainly driven by the surface-tension force based on the contact angle between bumps and substrate. On the other hand, the propagation of the melt front is mainly dominated by the dispensing design of underfill and the distribution of micro bumps. For the simulation of dispensing behavior, 3D modeling is unavoidable. However, the computing cost will become unaffordable due to the number of bumps. To ease the computing cost, an equivalent technique -The Equivalent Bump Group (EBG) model is proposed to the simulation. A simple package is studied to validate the proposed methodology. The case shows that the modeling solution of melt front by EBG model has a good agreement to the detailed model by according dispensing passes. Therefore, it is convinced that the proposed methodology provides a promising simulation solution for the microchip encapsulation for multi-chip packages with large number of micro bumps. A study for a multi-array package of different dispensing designs by EBG model is also conducted. The result shows that filling time can be predicted to get the best dispensing design with minimum filling time.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129362114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

RF Characterization on Nb-based Superconducting Silicon Interconnect Fabric for Future Large Scale Quantum Applications 面向未来大规模量子应用的铌基超导硅互连结构的射频特性研究

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00154

Yu-Tao Yang, Haoxiang Ren, S. Chong, Gang Qiu, Shu-Yun Ku, Yang Cheng, Chaowei Hu, Tiema Qian, Kuan-Neng Chen, Ni Ni, Kang L. Wang, S. Iyer

{"title":"RF Characterization on Nb-based Superconducting Silicon Interconnect Fabric for Future Large Scale Quantum Applications","authors":"Yu-Tao Yang, Haoxiang Ren, S. Chong, Gang Qiu, Shu-Yun Ku, Yang Cheng, Chaowei Hu, Tiema Qian, Kuan-Neng Chen, Ni Ni, Kang L. Wang, S. Iyer","doi":"10.1109/ectc51906.2022.00154","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00154","url":null,"abstract":"To preserve delicate quantum signals (few hundreds to a few tens of µV), low-loss and low-crosstalk inter-dielet communication is a must in a wafer-scale integrated quantum system using Superconducting-IF. In this paper, inter-dielet links (short: 125 μm and 500 μm; long: 1750 μm) with L/S (2/2 and 5/5 μm) are characterized in a broadband 20 GHz range through simulation and experiments at 4K A compact assembly (inter-dielet spacing of 100 μm) through the quantum-compatible fine-pitch (10 um) Au interlayer is conducted. For insertion loss and crosstalk characterization, the simulated and measured results are presented to be low-loss (<1 dB) and low-crosstalk (< -23 dB) in the broadband 20 GHz range with short (≤ 500 um) and long (1750 um) links and two L/S (2/2 and 5/5 um). It is one of the first 20 GHz broadband RF characterization of short superconducting links (≤ 500 um) through advanced packaging for cryogenic inter-dielet quantum communication. This work brings large-scale quantum computing closer to being realized through compact heterogeneous integration.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129429042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mechanical simulation and modeling for reliability of 6-in-1 power module 6合1电源模块可靠性力学仿真与建模

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00258

Rathin Mandal, Kazunori Yamamoto, G. Tang

{"title":"Mechanical simulation and modeling for reliability of 6-in-1 power module","authors":"Rathin Mandal, Kazunori Yamamoto, G. Tang","doi":"10.1109/ectc51906.2022.00258","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00258","url":null,"abstract":"numerical modeling and simulation of temperature cycling test (TCT) and power cycling test (PCT) are applied to the design reliability analysis for a proposed 6-in-1 power module (PM) package. The fatigue life for both 95Sn5Sb solder interconnect and sintered Ag die attach (DA) joints under TCT and PCT conditions are calculated and compared with a reference power module package which has already passed the reliability test. The Coffin-mansion life model ductility factor is calculated from the test data for the reference power module and applied to the analysis of the fatigue life for the PM. The reliability of solder interconnect is in the same level as the reference module which passed the 1000 cycles of TCT and 50000 cycles of PCT. Sintered Ag DA joint has a very high reliability life. The structural reliability of interconnect for the proposed PM could be further enhanced by using sintered Ag as both DA and interconnect materials. Effect of package parameters such as DA and copper clip thickness are also investigated in this study. The results provided important guidelines for the PM package design.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Co-design of Thermal Management with System Architecture and Power Management for 3D ICs 3D集成电路的热管理与系统架构和电源管理协同设计

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00044

Rishav Roy, Shidhartha Das, Benoît Labbé, R. Mathur, Supreet Jeloka

引用次数: 2

Yield Improvement in Chip to Wafer Hybrid Bonding 晶片-晶片混合键合的良率提升

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00311

Ser Choong Chong, Ismael Cereno Daniel, S. Lim Pei Siang, Joseph Shim Cheng Yi, Alvin Lai Wai Song, Woon Leng Loh

{"title":"Yield Improvement in Chip to Wafer Hybrid Bonding","authors":"Ser Choong Chong, Ismael Cereno Daniel, S. Lim Pei Siang, Joseph Shim Cheng Yi, Alvin Lai Wai Song, Woon Leng Loh","doi":"10.1109/ectc51906.2022.00311","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00311","url":null,"abstract":"Chip to Wafer Hybrid Bonding is an attractive way to achieve ultra-fine pitch interconnect down to 6μm. Conventional way such as solder interconnects has issues of solder merging, underfill voids, and weak intermetallic solder joints that unable to implement in ultra-fine pitch interconnects.Hybrid Bonding itself also has many issues such as Cu dishing or protrusion, oxide surface roughness and the cleanliness of the bonding surface. Singulation process is known to introduce particles such as silicon debris on the wafer’s surface. A protective layer is deposited on the wafer before the singulation process to prevent the silicon debris from sticking on the wafer’s surface. Detail optimization of cleaning process involving different protective layer and cleaning parameters were done. Yield of the diced wafer with respect to the cleanliness of the wafer’s surface has improved with optimized cleaning parameters and the right protective layer. The improved cleaning process was adopted in the preparation of the diced wafer for chip to wafer bonding. The study clearly showed that the void has drastically reduced to less than 3% in the diced wafer prepared with protective layer as compared to range of 0.2 to 91% voids for the diced wafer prepared without protective layer.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"84 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127978586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Antenna-Integrated, Die-Embedded Glass Package for 6G Wireless Applications 天线集成，芯片嵌入玻璃封装6G无线应用

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00069

Xiaofan Jia, Xingchen Li, K. Moon, Joon Woo Kim, Kai-Qi Huang, M. Jordan, Madhavan Swaminathan

{"title":"Antenna-Integrated, Die-Embedded Glass Package for 6G Wireless Applications","authors":"Xiaofan Jia, Xingchen Li, K. Moon, Joon Woo Kim, Kai-Qi Huang, M. Jordan, Madhavan Swaminathan","doi":"10.1109/ectc51906.2022.00069","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00069","url":null,"abstract":"This work presents the implementation and characterization of a die-embedded, antenna-integrated glass package for RF modules in D-Band. The proposed package uses glass as the core material which can match the coefficient-of-thermal-expansion (CTE) well for RF chips and printed circuit board (PCB). The redistribution layer (RDL) for electrical connections is built on low-loss polymeric build-up dielectric films (ABF-GL102). Dummy dies are embedded in the glass cavities for characterization. The interconnects between die pads and the package are implemented using micro-vias. An 8-elements series-fed microstrip patch antenna is also integrated on the low-loss RDL. The proposed glass panel embedded package addresses the electrical loss and parasitic from the interconnects. With micro-vias and transmission lines built on low-loss RDL, the glass embedded package provides low-loss and low-parasitic chip-to-chip and chip-to-antenna interconnects. Using temporary thermal release tapes, this package also shows great potential to address the high heat dissipation from D-band power amplifiers.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123173463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Demonstration of Glass-based 3D Package Architectures with Embedded Dies for High Performance Computing 基于玻璃的3D封装架构与嵌入式芯片的高性能计算演示

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00180

Siddharth Ravichandran, V. Smet, Madhavan Swaminathan, R. Tummala

引用次数: 1

Stability Analysis of Nanoscale Copper-Carbon Hybrid Interconnects 纳米级铜碳杂化互连的稳定性分析

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00158

B. Kumari, Rohit Sharma, Manodipan Sahoo

{"title":"Stability Analysis of Nanoscale Copper-Carbon Hybrid Interconnects","authors":"B. Kumari, Rohit Sharma, Manodipan Sahoo","doi":"10.1109/ectc51906.2022.00158","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00158","url":null,"abstract":"Copper Carbon (Cu-Carbon) hybrid interconnect is a new and an extremely promising candidate for future VLSI circuit applications, so it needs to be analyzed for not only propagation delay but its stability should also be examined in order to consolidate its claim as an alternative to existing interconnect configurations. In this work, stability analysis of the recently proposed Cu-Carbon hybrid interconnect is performed and compared with existing alternate hybrid interconnect candidates (i.e. copper, copper-graphene hybrid and copper-carbon nanotube composite). A three-line coupled interconnect system for 7 nm technology node is considered in this study whose dimensional parameters are adopted as per the IRDS roadmap guidelines. The unit-step response of Cu-Carbon hybrid interconnect is steepest as compared to others because of its lowest switching delay. Cu-Carbon hybrid appears to be the most stable as its nyquist plot intersects farthest from the critical point (-1, j0) towards origin. The effect of crosstalk leads to undershoots as seen in the time domain response of copper interconnects, but it does not have any notable effect on Cu-Carbon hybrid interconnects. It is evident that as the fraction of carbon nanotube in Cu-Carbon hybrid (Fcnt) increases, bandwidth increases due to decrease in resistance. Also, Cu-Carbon with Fcnt = 0.8 is most stable amongst all configurations. We conclude that Cu-Carbon hybrid is the most stable candidate among all the alternative interconnect configurations, claiming it to be a desirable interconnect alternative for near-future VLSI applications.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125916534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2