2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)最新文献_第10页

The investigation of dry plasma technology in each steps for the fabrication of high performance redistribution layer 研究了干等离子体技术制备高性能重分布层的各个步骤

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00308

Daisuke Hironiwa, Haw Wen Chen, Y. Morikawa, Takashi Kurimoto, R. Kamimura

引用次数: 0

Solder Joint Fatigue Studies Subjected to Board-level Random Vibration for Automotive Applications 汽车用板级随机振动下焊点疲劳研究

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00280

Valeriy Khaldarov, Andy Zhang, Dongji Xie, J. Lee, Xue Shi, R. Roucou, S. Doranga, A. Shalumov

{"title":"Solder Joint Fatigue Studies Subjected to Board-level Random Vibration for Automotive Applications","authors":"Valeriy Khaldarov, Andy Zhang, Dongji Xie, J. Lee, Xue Shi, R. Roucou, S. Doranga, A. Shalumov","doi":"10.1109/ectc51906.2022.00280","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00280","url":null,"abstract":"In this paper, a simplified methodology is presented for the evaluation of test-to-failure board-level random vibrations using a combination of experimental and finite element modeling techniques in calculating equivalent stresses for SAC305 solder joints experiencing high- and ultra-high-cycle fatigue usually found in the emerging automotive robo-taxi industry. Some partial results that were obtained during this study allow for an investigation of the effects of a printed circuit board geometry on possible failure modes of Pb-free solder joints. These results seem to confirm the findings that have been reported previously by some researchers on the migration of a failure mode from the ductile fracture in the bulk solder to the brittle fracture of the intermetallic compound (IMC) layer due to the positive correlation between the tensile strength of the solder joint and the strain rate which may have occurred from high level of vibration and shock during the test. The generated data points were then compared to the existing S-N (stress-life) fatigue curves for the SAC305 solder joints in order to assess whether these curves can provide adequate results for the test vehicles fatigue life calculations. These preliminary results show that more work is needed in both verifying the effect of a failure mode migration in the solder joints as well as developing additional data points for S-N curve generation. This research is a continuation of the study initiated by the JEDEC JESD22 working group.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130330408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Novel Packaging Platform for High-Performance Optical Engines in Hyperscale Data Center Applications 超大规模数据中心应用中高性能光引擎的新型封装平台

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00074

Sajay Bhuvanendran Nair Gourikutty, M. C. Jong, Chockanathan Vinoth Kanna, D. Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, T. Lim, Rathin Mandal, J. Liow, S. Bhattacharya

{"title":"A Novel Packaging Platform for High-Performance Optical Engines in Hyperscale Data Center Applications","authors":"Sajay Bhuvanendran Nair Gourikutty, M. C. Jong, Chockanathan Vinoth Kanna, D. Ho, Seit Wen Wei, Sharon Lim Pei Siang, Jiaqi Wu, T. Lim, Rathin Mandal, J. Liow, S. Bhattacharya","doi":"10.1109/ectc51906.2022.00074","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00074","url":null,"abstract":"Due to the increase in the amount of data handled and evolving data center architectures, there is a growing demand to use high-performance optical transceivers within and between the data centers. We propose a new heterogeneous packaging platform for optical transceivers that can handle higher data rates addressing cost, performance, and form-factor requirements. In this paper, the proof of concept is demonstrated by developing a passive optical engine package with a size of 11mmx11mm integrating electronic and photonic chips. To realize this, a fan-out wafer-level packaging method is employed that can provide high-speed electrical interconnects and integrated photonic chip with suspended optical couplers. By employing this platform, discrete chiplets can be optimized independently and integrated into small-form-factor packages that are otherwise not possible with monolithic integration and provide a clear differentiation compared to other approaches currently in the industry.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"933 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116632129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Co-design and Signal-Power Integrity/EMI Co-analysis of a Switchable High-speed Inter-Chiplet Serial Link on an Active Interposer 主动式中介器上可切换高速芯片间串行链路的协同设计和信号功率完整性/EMI协同分析

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00214

M. Miao, Xiaolong Duan, Liang Sun, Tao Li, Shiliang Zhu, Zhuanzhuan Zhang, Jin Li, Danya Zhang, Hao Wen, Xuena Liu, Zhensong Li

{"title":"Co-design and Signal-Power Integrity/EMI Co-analysis of a Switchable High-speed Inter-Chiplet Serial Link on an Active Interposer","authors":"M. Miao, Xiaolong Duan, Liang Sun, Tao Li, Shiliang Zhu, Zhuanzhuan Zhang, Jin Li, Danya Zhang, Hao Wen, Xuena Liu, Zhensong Li","doi":"10.1109/ectc51906.2022.00214","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00214","url":null,"abstract":"This paper proposes a chiplet-based domain specific architecture (DSA) module on active interposer for convolutions in various scenarios. By constructing an integral development frame, the I/O and inter-chiplet links behaviors together with signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) issues can be co-considered and co-analyzed in the early phases, facilitating efficient implementation of heterogeneous integration. Additionally, the proposed solution takes advantage of the flexibility of a novel network-on-chip (NoC) switching fabric for inter-chiplet data exchange and versatile auxiliary circuitry enabled by an active interposer, to enhance its performance and extend the scope of application. The design and analysis results are shown, as well as associated options and potentials of the development frame. Up to now, the prototype chip samples for the switching fabric has been delivered by foundry; detailed physical design and assembly of the DSA module with off-the-shell dies and cost- effective Si interposer solution are under way.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Mechanical simulation and modeling for reliability of 6-in-1 power module 6合1电源模块可靠性力学仿真与建模

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00258

Rathin Mandal, Kazunori Yamamoto, G. Tang

{"title":"Mechanical simulation and modeling for reliability of 6-in-1 power module","authors":"Rathin Mandal, Kazunori Yamamoto, G. Tang","doi":"10.1109/ectc51906.2022.00258","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00258","url":null,"abstract":"numerical modeling and simulation of temperature cycling test (TCT) and power cycling test (PCT) are applied to the design reliability analysis for a proposed 6-in-1 power module (PM) package. The fatigue life for both 95Sn5Sb solder interconnect and sintered Ag die attach (DA) joints under TCT and PCT conditions are calculated and compared with a reference power module package which has already passed the reliability test. The Coffin-mansion life model ductility factor is calculated from the test data for the reference power module and applied to the analysis of the fatigue life for the PM. The reliability of solder interconnect is in the same level as the reference module which passed the 1000 cycles of TCT and 50000 cycles of PCT. Sintered Ag DA joint has a very high reliability life. The structural reliability of interconnect for the proposed PM could be further enhanced by using sintered Ag as both DA and interconnect materials. Effect of package parameters such as DA and copper clip thickness are also investigated in this study. The results provided important guidelines for the PM package design.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A comparative study of the thermomechanical reliability of fully-filled and conformal through-glass via 满填充与保形玻璃通孔热机械可靠性的比较研究

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00194

K. Pan, C. Okoro, Yangyang Lai, Dhananjay Joshi, Seungbae Park, S. Pollard

引用次数: 6

Slot Bow-Tie Antenna Integration in Flip-Chip and Embedded Die Enhanced QFN Package for WR8 and WR5 Frequency Bands WR8和WR5频段倒装芯片和嵌入式芯片增强QFN封装槽领结天线集成

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00068

Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Tony Tang, R. Murugan, Hassan Ali

{"title":"Slot Bow-Tie Antenna Integration in Flip-Chip and Embedded Die Enhanced QFN Package for WR8 and WR5 Frequency Bands","authors":"Aditya N. Jogalekar, Oscar F. Medina, A. Blanchard, R. Henderson, M. Iyer, Tony Tang, R. Murugan, Hassan Ali","doi":"10.1109/ectc51906.2022.00068","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00068","url":null,"abstract":"Antenna-in-Package (AiP) has emerged as a mainstream technology for millimeter-wave (mmWave) front-end modules driving it to meet future requirements. This paper discusses, for the first time, the design, modeling, and characterization of a slot bow-tie antenna (SBT) integrated into an embedded die enhanced quad flat no-lead (EDeQFN) package along with a comparison of a flip-chip version of the eQFN in WR8 (90GHz-140GHz) and WR5 (140GHz-220GHz) frequency bands. Further, a brief description of the design, modeling, and simulation results of mmWave chip-to-package transitions, transmission line structures, and antenna feed elements are provided. The insertion and return losses of these structures are less than 1.07dB and greater than 17dB, respectively for FCeQFN, less than 0.87dB, and greater than 22dB, respectively for EDeQFN package. The bandwidth and gain of the integrated SBT antenna in the above packages are 40GHz and 80GHz, with a peak gain of 7dBi and 7.7dBi in the WR8 and WR5 band, respectively. A brief description of the designed test vehicles, probing and measurement methodology for antenna bandwidth, and radiation pattern characterization in the WR5 frequency band is also presented.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131674674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

The Integration of Grounding Plane into TSV Integrated Ion Trap for Efficient Thermal Management in Large Scale Quantum Computing Device 大规模量子计算设备中TSV集成离子阱的高效热管理

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00032

P. Zhao, Hong Yu Li, Yu Dian Lim, W. Seit, L. Guidoni, C. S. Tan

引用次数: 1

Machine Learning Assisted Counterfeit IC Detection through Non-destructive Infrared (IR) Spectroscopy Material Characterization 通过非破坏性红外(IR)光谱材料表征，机器学习辅助伪造IC检测

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00355

Chengjie Xi, Nathan Jessurun, John True, Aslam A. Khan, M. Tehranipoor, N. Asadizanjani

{"title":"Machine Learning Assisted Counterfeit IC Detection through Non-destructive Infrared (IR) Spectroscopy Material Characterization","authors":"Chengjie Xi, Nathan Jessurun, John True, Aslam A. Khan, M. Tehranipoor, N. Asadizanjani","doi":"10.1109/ectc51906.2022.00355","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00355","url":null,"abstract":"Nowadays, counterfeit integrated circuits (IC) are increasingly common due to the continuous growth of supply chain globalization. This supply chain vulnerability results in unreliable and insecure counterfeit ICs integrated into the end-user devices in many applications, including consumer, corporate, and military domains. Various methods such as aging detection sensors, Physical Unclonable Functions (PUFs), and hardware metering have been developed to detect such counterfeits before they become integrated into critical systems. However, several complicated aspects of detection and prevention limit their use as a stopgap to the counterfeit problem. Hence, there is a critical need for novel inspection and assurance techniques that require minimal or no additional changes/modifications to the device circuit or material while remaining low-cost per sample. In this paper, the possibility of using IC packaging material characterization for counterfeit detection is proved by a preliminary material survey between the counterfeit and authentic ICs. Diffuse Reflectance Infrared Fourier Transform Spectroscopy (DRIFT) is used as the material characterization in this research, and the material spectrums will be utilized for training machine learning classification models. Several machine learning classification methods will be tested, such as Linear discriminant analysis (LDA), Support Vector Machine (SVM), random forest(RF), and multi-layer perceptron (MLP). With the help of the Standard Normal Variate (SNV) data preprocessing and MPL model, over 92 percent accuracy of counterfeit versus genuine sample discrimination has been achieved. This proves the existence of packaging material differences between counterfeit and authentic IC samples.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132322210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

System Level Power Supply Induced Jitter Suppression for multi-lane high speed serial links 多通道高速串行链路的系统级电源诱发抖动抑制

2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Pub Date : 2022-05-01 DOI: 10.1109/ectc51906.2022.00293

Goeun Kim, Doohee Lim, Tamal Das, Eunjung Lee, S. You

{"title":"System Level Power Supply Induced Jitter Suppression for multi-lane high speed serial links","authors":"Goeun Kim, Doohee Lim, Tamal Das, Eunjung Lee, S. You","doi":"10.1109/ectc51906.2022.00293","DOIUrl":"https://doi.org/10.1109/ectc51906.2022.00293","url":null,"abstract":"This paper presents a system-level co-optimization approach with Chip Power Model based power integrity simulation of the power delivery network and jitter sensitivity transfer function (JTF). Due to the need to merge multiple power domains and to locate adjacent power domains close to each other for enhancing cost effectiveness and space efficiency, the coupling resonance severely affects the whole system. To meet the rigorous performance requirements, a system-level co-design is mandatory. An approach which analyzes the V-by-One IP circuit blocks and finds the critical path based on the JTF is suggested within the case studies. An on-chip level optimization to bring higher voltage controlled oscillator output frequency and to add sufficient On-die-cap was analyzed. In the off-chip design stage, various design modifications to split the power domain, reinforce the ground path, and add package decoupling capacitors were attempted to decrease total jitter by the JTF. Finally, a co-optimization design process workflow which controls the total jitter budgeting is presented. The total jitter is decreased by 68.49% compared to the worst design case.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":"79 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132330703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4