Yield Improvement in Chip to Wafer Hybrid Bonding

Abstract

Chip to Wafer Hybrid Bonding is an attractive way to achieve ultra-fine pitch interconnect down to 6μm. Conventional way such as solder interconnects has issues of solder merging, underfill voids, and weak intermetallic solder joints that unable to implement in ultra-fine pitch interconnects.Hybrid Bonding itself also has many issues such as Cu dishing or protrusion, oxide surface roughness and the cleanliness of the bonding surface. Singulation process is known to introduce particles such as silicon debris on the wafer’s surface. A protective layer is deposited on the wafer before the singulation process to prevent the silicon debris from sticking on the wafer’s surface. Detail optimization of cleaning process involving different protective layer and cleaning parameters were done. Yield of the diced wafer with respect to the cleanliness of the wafer’s surface has improved with optimized cleaning parameters and the right protective layer. The improved cleaning process was adopted in the preparation of the diced wafer for chip to wafer bonding. The study clearly showed that the void has drastically reduced to less than 3% in the diced wafer prepared with protective layer as compared to range of 0.2 to 91% voids for the diced wafer prepared without protective layer.