2008 International Conference on Field Programmable Logic and Applications最新文献_第3页

Performance optimization by track swapping on critical paths utilizing random variations for FPGAS 利用fpga的随机变化在关键路径上进行跟踪交换的性能优化

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629994

Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, H. Onodera

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引用次数: 3

Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory 循环调度和分配最小化能量，同时隐藏异构多银行内存的延迟

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629983

Meikang Qiu, Jiande Wu, C. Xue, J. Hu, Wei-Che Tseng, E. Sha

引用次数: 2

A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor 动态可重构处理器中用于模块化特殊指令的一种计算和通信基础结构

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629932

L. Bauer, M. Shafique, J. Henkel

{"title":"A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor","authors":"L. Bauer, M. Shafique, J. Henkel","doi":"10.1109/FPL.2008.4629932","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629932","url":null,"abstract":"Processors with a reconfigurable instruction set combine the performance of dedicated application accelerators with a flexibility that goes beyond that of traditional application specific instruction set processors (ASIPs). The latter are optimized for certain application domains and thus typically do not provide a high performance and/or efficiency when deployed in other domains. State-of-the-art reconfigurable processors on the other side still use the concept of monolithic Special Instructions (SIs, i.e. the application accelerators). In our work, we instead present modular SIs as a hierarchy of elementary data paths and different SI implementations that facilitate a high flexibility and performance. This is a novel concept that achieves a speedup of 26.6x compared to a general purpose processor and 1.24x compared to a state-of-the-art reconfigurable processor (that is statically optimized for the predetermined benchmark situation) when executing an H.264 video encoder. We introduce a novel infrastructure for computation and communication that actually enables the implementation of modular SIs and offers various parameters to match specific requirements. The infrastructure is implemented and tested on an FPGA-based prototype to demonstrate its feasibility.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"49 17","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114006334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Acceleration of a production rigid molecule docking code 一个生产刚性分子对接代码的加速

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629955

Bharat Sukhwani, M. Herbordt

引用次数: 17

File system access from reconfigurable FPGA hardware processes in BORPH BORPH中可重构FPGA硬件进程的文件系统访问

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630010

Hayden Kwok-Hay So, R. Brodersen

引用次数: 16

Combating process variation on FPGAS with a precise at-speed delay measurement method 用一种精确的高速延迟测量方法对抗fpga上的工艺变化

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630046

Justin S. J. Wong, P. Cheung, N. P. Sedcole

引用次数: 5

SAT-based resource binding for reducing critical path delays 用于减少关键路径延迟的基于sat的资源绑定

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629995

Kenshu Seto, Yuta Nonaka, T. Maruizumi, Y. Shiraki

引用次数: 2

An element-by-element preconditioned Conjugate Gradient solver of 3D tetrahedral finite elements on an FPGA coprocessor 基于FPGA协处理器的三维四面体有限元单元预条件共轭梯度求解器

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630012

Jing Hu, S. Quigley, A. Chan

引用次数: 9

No-break dynamic defragmentation of reconfigurable devices 可重构设备的无中断动态碎片整理

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629917

S. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, J. V. D. Veen, Josef Angermeier, Dirk Koch, J. Teich

引用次数: 17

FPGA acceleration of Monte-Carlo based credit derivative pricing 基于蒙特卡罗的信用衍生品定价的FPGA加速

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629953

Alexander Kaganov, P. Chow, A. Lakhany

引用次数: 34