2009 IEEE Computer Society Annual Symposium on VLSI最新文献_第4页

Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations 具有延迟变化的CMOS电路中故障数和动态功率估计算法

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.57

Jins D. Alexander, V. Agrawal

{"title":"Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations","authors":"Jins D. Alexander, V. Agrawal","doi":"10.1109/ISVLSI.2009.57","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.57","url":null,"abstract":"Dynamic power dissipation of a CMOS VLSI circuit depends on the signal activity at gate outputs. The activity includes the steady-state logic transitions as well as glitches. The latter are a function of gate delays, which, for modern VLSI circuits, have wide process-related variations. Both average and peak power dissipation are useful and are traditionally estimated by Monte Carlo simulation. This is expensive and the accuracy, especially for peak power,depends upon the number of circuit delay samples that are simulated. We present an alternative. We use zero-delay simulation of a vector pair to determine the steady-state logic activity. We derive linear-time algorithms that, using delay bounds for gates, determine the maximum, minimum and average number of transitions that each gate output can produce. From this information, we estimate the average and peak energy consumed by each vector pair in a given vector set. For a set of random vectors applied to c7552 circuit, our analysis determined the per-vector energy consumption as 82.2 picojoules average and 196.3 picojoules peak. In comparison, Monte Carlo simulation of 1,000 circuit samples gave 82.8 picojoules average and 146.1 picojoules peak. The discrepancy of the peak consumption will reduce if more samples were simulated in the Monte Carlo method. Even with 1,000 samples the CPU time of the Monte Carlo analysis was three orders of magnitude greater than the alternative method we offer in this paper.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"176 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120954213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design VLSI物理设计中IP标记的安全防漏公开验证

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.35

Debasri Saha, S. Sur-Kolay

引用次数: 2

A Process Variation Tolerant Self-Compensating Sense Amplifier Design 一种过程容差自补偿感测放大器设计

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.50

A. Choudhary, S. Kundu

引用次数: 14

Context-aware Post Routing Redundant Via Insertion 上下文感知后路由冗余通过插入

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.39

P. Chu, Rung-Bin Lin, Da-Wei Hsu, Yu-Hsing Chen, Wei-Chiu Tseng

引用次数: 1

Modern Floorplanning with Boundary Clustering Constraint 具有边界聚类约束的现代平面规划

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.24

Li Li, Yuchun Ma, N. Xu, Yu Wang, Xianlong Hong

引用次数: 1

Reduction of Current Mismatch in PLL Charge Pump 锁相环电荷泵电流失配的减小

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.45

H. Fazeel, L. Raghavan, Chandrasekaran Srinivasaraman, Manish Jain

引用次数: 17

A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications 一种适用于低功耗应用的新型低面积开销体偏置FPGA架构

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.51

Sungmin Bae, K. Ramakrishnan, N. Vijaykrishnan

{"title":"A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications","authors":"Sungmin Bae, K. Ramakrishnan, N. Vijaykrishnan","doi":"10.1109/ISVLSI.2009.51","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.51","url":null,"abstract":"As technology scales, leakage power shares a dominant part in the total power dissipation of the chip and reaches up to 50% or even higher at elevated temperatures in 45 nm technology. Leakage power dissipation is especially problematic for FPGAs due to their reconfigurable nature and large number of inactive resources. Body biasing is an efficient technique to reduce leakage current which has been widely adopted in 45nm technology low power architectures.FPGAs with coarse grained body bias control only incurred about 10% of the area overhead while increasing the granularity to the finest level dramatically increases the area overhead over 100%. However, the coarse grained body bias control FPGA may not result in satisfactory leakage power reduction since all the paths passing a resource must have enough slacks. To overcome the assignment limitation, we propose a novel FPGA architecture which uses body biasing technique and clock skew scheduling at a coarse grained architecture level. Clock skew scheduling technique only incurs 3.35% of additional area overhead in order to distribute slack to the resource instead of increasing the minimum body-bias granularity. Further, we propose a body bias assignment algorithm to leverage the proposed architecture. Experimental results demonstrate that the proposed architecture achieved an average leakage reduction of about 76% as compared to 61% of coarse grained architecture.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115133579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor 片式多处理器核与缓存间最优区域分解的解析模型

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.27

Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho

引用次数: 34

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise 考虑电源门控感应功率/地噪声的MPSoC在线调度

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.54

Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang

{"title":"On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise","authors":"Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang","doi":"10.1109/ISVLSI.2009.54","DOIUrl":"https://doi.org/10.1109/ISVLSI.2009.54","url":null,"abstract":"Power gating induced power/ground(P/G) noise is a major reliability problem facing by low power MPSoCs using power gating techniques. Powering on and off a process unit in MPSoCs will induce large P/G noise and can cause timing divergence and even functional errors in surrounding processing units. P/G noise is different from thermal or energy which is an accumulative effect. The noise level should be predicted and victim circuits should be protected before the noise is induced. hence, the power gating-aware scheduling problem with the consideration of P/G noise should be solved using an on-line method considering the run-time variation of tasks' execution time. In this paper, we formulate an on-line task scheduling problem with the consideration of P/G noise based on our detailed P/G noise analysis platform for MPSoC. An efficient on-line Greedy Heuristic (GH) algorithm that adapts well to real-time variation is proposed to reduce noise protection penalty and improve MPSoC performance. Our experiments show that the algorithm can achieve an average 26% performance improvement together with an average 73% noise protection penalty saving compared with the conservative stop-go method. We also compare our technique with a two-step solution that computes a static schedule at compile time and make adjustment on the schedule according to runtime variations. For benchmark with larger task number, GH method achieves impressive performance improvement comparing with the two-step solution.","PeriodicalId":137508,"journal":{"name":"2009 IEEE Computer Society Annual Symposium on VLSI","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132230358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Lossless Compression Using Efficient Encoding of Bitmasks 使用有效的位掩码编码的无损压缩

2009 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2009-05-13 DOI: 10.1109/ISVLSI.2009.18

C. Murthy, P. Mishra

引用次数: 10